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EditSteps

  1. Tcl with Modelsim Step 1.png
    1
    Click on File > New > Source > Do.
    • Note that the design file needs to be added before adding a TCL file.
  2. Tcl with Modelsim Step 2.png
    2
    Paste the code and make the changes required.
  3. 3
    Create a library.
    • vlib work
    • vmap work work
  4. 4
    Compile the counter verilog code and add the file extension of the file.
    • vlog counter.v
  5. 5
    Load it for simulation. Use only the module name.
    • vsim counter
  6. 6
    Open some selected windows for viewing.
    • view structure
    • view signals
    • view wave
  7. 7
    Show some of the signals in the wave window.
    • add wave
  8. 8
    Force the signals with logic values 0 or 1.
    • force rst 1
    • force rst 0
    • run
  9. Tcl with Modelsim Step 3.png
    9
    Save the file as any_name.tcl in the same working directory.
  10. Tcl with Modelsim Step 4.png
    10
    In the Transcript window type the command do any_name.tcl.
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Article Info

Categories: Summarization

Recent edits by: WritingEnthusiast14, Lucky_JY, Basheera.A

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