Cache invalidation

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Cache invalidation is a process whereby entries in a cache are deleted. It can be done explicitly, as part of a cache coherence protocol in a parallel computer. In such a case, a compute node changes a variable and then invalidates the cached values of that variable across the rest of the computer system.

v t e Parallel computing

General	Cloud computing High-performance computing Cluster computing Distributed computing Grid computing

Levels	Bit Instruction Data Memory Task

Multithreading	Temporal multithreading Simultaneous multithreading Hyper-threading

Theory	PRAM model Analysis of parallel algorithms Amdahl's law Gustafson's law Cost efficiency Karp–Flatt metric Slowdown Speedup

Elements	Process Thread Fiber Instruction window

Coordination	Multiprocessing Memory coherency Cache coherency Cache invalidation Barrier Synchronization Application checkpointing

Programming	Models Implicit parallelism Explicit parallelism Concurrency Flynn's taxonomy SISD SIMD MISD MIMD SPMD Thread Non-blocking algorithm

Hardware	Multiprocessor Symmetric Asymmetric Memory NUMA COMA distributed shared distributed shared MPP Superscalar Vector processor Supercomputer Beowulf cluster

APIs	Ateji PX POSIX Threads OpenMP OpenHMPP OpenACC PVM MPI UPC TBB Boost.Thread Global Arrays Charm++ Cilk/Cilk Plus Coarray Fortran OpenCL CUDA Dryad C++ AMP PLINQ TPL

Problems	Embarrassingly parallel Software lockout Scalability Race condition Deadlock Livelock Starvation Deterministic algorithm Parallel slowdown

Category: parallel computing Media related to parallel computing at Wikimedia Commons