Video Codec Engine

Video Codec Engine (VCE) is the name given to AMD's video encoding ASIC implementing the video codec H.264/MPEG-4 AVC. It integrated into some of their GPUs and APUs.

Video Codec Engine was introduced with the Radeon HD 7900 on 22 December 2011. VCE occupies a considerable amount of the die surface and is not to be confused with AMD's Unified Video Decoder (UVD).

Overview

In "fixed mode" the entire computation is done by the fixed-function VCE unit. Fixed mode can be accessed through the OpenMAX IL API.

The entropy encoding block of the VCE ASIC is also separately accessible, enabling "hybrid mode". In "hybrid mode" most of the computation is done by the 3D engine of the GPU. Using AMD's Accelerated Parallel Programming SDK and OpenCL developers can create hybrid encoders that pair custom motion estimation, inverse discrete cosine transform and motion compensation with the hardware entropy encoding to achieve faster than real-time encoding.

The handling of video data involves computation of data compression algorithms and possibly of video processing algorithms. As the template Compression methods shows, lossy video compression algorithms involve the steps: Motion estimation (ME), Discrete cosine transform (DCT), and entropy encoding (EC).

AMD Video Codec Engine (VCE) is a full hardware implementation of the video codec H.264/MPEG-4 AVC. The ASIC is capable of delivering 1080p at 60 frames/sec. Because its entropy encoding block is also separately accessible Video Codec Engine can be operated in two modes: full mode and hybrid mode.

By emyploing AMD APP SDK, available for Linux and Microsoft Windows, developers can create hybrid encoders that pair custom motion estimation, inverse discrete cosine transform and motion compensation with the hardware entropy encoding to achieve faster than real-time encoding. In hybrid mode, only the entropy encoding block of the VCE unit is used, while the remaining computation is offloaded to the 3D engine (GCN) of the GPU, so the computing scales with the number of available compute units (CUs).

VCE 1.0

As of April 2014, there are two versions of VCE. Version 1.0 supports H.264 YUV420 (I & P frames), H.264 SVC Temporal Encode VCE, and Display Encode Mode (DEM).

It can be found on

• Piledriver-based
  • Trinity APUs (Ax - 5xxx, e.g. A10-5800K)
  • Richland APUs (Ax - 6xxx, e.g. A10-6800K)
• GPUs of the Southern-Island-Generation. These are
  • Radeon HD7700 series
  • Radeon HD7800 series
  • Radeon HD7900 series
  • Radeon R7 250X
  • Radeon R9 270 / 270X
  • Radeon R9 280 / 280X

VCE 2.0

Compared to the first version, VCE 2.0 adds H.264 YUV444 (I-Frames), B-frames for H.264 YUV420, and improvements to the DEM (Display Encode Mode), which results in a better encoding quality.

It can be found on

• Steamroller-based
  • Kaveri APUs (Ax - 7xxx, e.g. A10-7850K)
• Jaguar-based
  • Kabini APUs (e.g. Athlon 5350, Sempron 2650)
  • Temash APUs (e.g. A6-1450, A4-1200)
• Puma-based
  • Beema and Mullins
• GPUs of the Sea-Islands-Generation as well Bonaire or Hawaii GPUs, such as
  • Radeon R7 260 / 260X
  • Radeon R9 290 / 290X
  • Radeon R9 295X2

Feature overview

The entire AMD Accelerated Processing Unit lines and some of their features

Brand	Brazos (low power)	Llano	Trinity	Richland	Kabini & Temash (low power)	Kaveri	Beema & Mullins (low power)	Carrizo	Carrizo-L (low power)
Released	Jan 2011	Aug 2011	Oct 2012	2013	May 2013	Jan 2014	Q2 2014	2015	2015
Fab (nm)	TSMC 40 nm	GlobalFoundries 32 nm SOI			28	28	28	28	28
APU Socket	FT1	FM1 FS1	FM2 FS1+ FP2		AM1 FT3	FM2+ FP3	FT3b	TBA	TBA
CPU cores	Bobcat	AMD 10h	Piledriver		Jaguar	Steamroller	Puma	Excavator	Puma+
3D engine1	80:8:4	400:20:8	384:24:6	384:24:6	128:8:4	512:32:8	128:8:4	TBA	TBA
	TeraScale 2 (VLIW5)		TeraScale 3 (VLIW4)		Graphics Core Next (Mantle, HSA)
	IOMMUv1					IOMMUv2	IOMMUv1	TBA	TBA
Unified Video Decoder	UVD 3				UVD 4	UVD 4.2		TBA	TBA
Video Codec Engine	N/A		VCE 1.0		VCE 2.0			TBA	TBA
TrueAudio	N/A					Yes	N/A	TBA	TBA
Max. № of displays2	2	2–3	2–4		2	2–4	2	TBA	TBA
Direct Rendering Manager/ Mesa 3D driver	Yes							WiP	WiP

• ¹ Unified shaders : Texture mapping units : Render output units
• ² To feed more than two displays, the additional panels must have native DisplayPort support. Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed

Operating system support

The VCE SIP core needs to be supported by the device driver. The device driver provides one or multiple interfaces, like e.g. OpenMAX IL. One of this interfaces is then used by end-user software, like e.g. GStreamer or HandBrake, to access the VCE hardware and make use of it.

AMD's proprietary device driver AMD Catalyst is available for multiple operating systems and support for VCE has been added to it. Additionally, a free device driver is available. This driver also supports the VCE hardware.

Linux

Support for the VCE ASIC is contained in the Linux kernel device driver amdgpu.

Main articles: AMD Catalyst for Linux and Free Radeon driver

• Initial VCE support has been added on 4 February 2014 by Kristian König of AMD to the free radeon driver.
• Gallium3D state tracker for OpenMAX was added 24 October 2013 to Mesa 3D.
• The free and open-source Radeon driver has been adapted to using OpenMAX with the GStreamer OpenMAX (gst-omx) support for exposing the VCE video encode engine.
• AMD employee Leo Liu implemented h264 level support into the Mesa 3D state tracker.

Windows

The software "MediaShow Espresso Video Transcoding" seems to utilize VCE and UVD to the fullest extent possible.

XSplit Broadcaster supports VCE from version 1.3

See also

• Intel Quick Sync Video, Intel's equivalent SIP core
• Nvidia NVENC, Nvidia's equivalent SIP core