Paddle Mobile Framework (移动端框架,支持多平台,高性能,低能耗预测部署)
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fpga
Repositories 1,052
An open source ecosystem for IoT development 👽 Cross-platform IDE and unified debugger. Remote unit testing and firmw…
GPGPU microprocessor architecture
C
Updated Mar 17, 2019
JavaScript
Updated Feb 13, 2019
A FPGA friendly 32 bit RISC-V CPU implementation
Assembly
Updated Mar 22, 2019
PlatformIO IDE for Atom: The next generation integrated development environment for IoT
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
C++
Updated Mar 11, 2019
Ariane is a 6-stage RISC-V CPU capable of booting Linux
SystemVerilog
Updated Mar 20, 2019
The USRP™ Hardware Driver Repository
C++
Updated Mar 19, 2019
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
Updated Feb 19, 2019
Scottish Army Knife for electronics
Python
Updated Mar 19, 2019
HDL libraries and projects
Verilog
Updated Mar 22, 2019
SpinalHDL core
Scala
Updated Mar 22, 2019
A small, light weight, RISC CPU soft core
Verilog
Updated Feb 14, 2019
FuseSoC is a package manager and a set of build tools for FPGA/ASIC development
Python
Updated Mar 19, 2019
VUnit is a unit testing framework for VHDL/SystemVerilog
Documenting the Xilinx 7-series bit-stream format.
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
Verilog
Updated Feb 3, 2018
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Com…
Verilog to Routing -- Open Source CAD Flow for FPGA Research
A Just-In-Time Compiler for Verilog from VMware Research
C++
Updated Mar 22, 2019
Generic system-wide modern C++ for heterogeneous platforms with SYCL from Khronos Group
FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's hi…
Haskell
Updated Feb 9, 2019
SDAccel Examples
C++
Updated Mar 1, 2019
A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
VHDL
Updated Mar 21, 2019
Python
Updated Mar 10, 2019
An open source library for image processing on FPGA.
Verilog
Updated Jun 16, 2015
KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
C++
Updated Mar 19, 2019
FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud (e.g. RISC-V Rocket …