CPU INFOrmation library (x86/x86-64/ARM/ARM64, Linux/Windows/Android/macOS/iOS)
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Jul 30, 2020 - Objective-C
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cpu-model
Here are 27 public repositories matching this topic...
Central Processing Unit Information Gathering Tool
security
cpu
system-information
cpuid
cpu-info
vulnerability-detection
cpu-model
security-tools
cpuinfo
linux-system
system-info
cpu-vulnerability
cpu-script
cpu-vulnerability-check
cpu-vulnerability-checker
cpu-security
intel-cpu
amd-cpu
intel-cpu-info
amd-cpu-info
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Jan 26, 2020 - Python
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Jul 22, 2019 - Verilog
A multi cycle RISC CPU (processor) like MIPS CPU in VHDL ( a hardware side code implementation )
processor-architecture
cpu
vhdl
isa
cpu-model
instruction-set-architecture
mips-processor
vhdl-modules
risc-processor
vhdl-code
cpu-architecture
multi-cycle
processor-design
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Jul 13, 2019 - VHDL
LatticeMico32 instruction set simulator project
linux
c-plus-plus
embedded
fpga
processor
gdb
iss
python3
tcp-socket
debug
tkinter
risc
cpu-model
32-bits
soft-core
serial-communication
latticemico32
com0com
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Sep 30, 2018 - C++
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Nov 21, 2018 - Verilog
One Instruction Set Computer
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Aug 18, 2017 - Python
CPU-based Radiosity: Final Team Project., testing - optimization & parallel skill
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Jan 18, 2017 - C++
Initial publish
visual-studio
fpga
csharp
stack
mapper
vhdl
microcode
cpu-model
microcode-updates
microcode-memory
instruction-register
machine-cycle
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Jul 2, 2020 - VHDL
Scheduling algorithms(Round Robin , Shortest Job First(preemptive - non preemptive))
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Apr 15, 2020 - Java
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Sep 2, 2017 - C
A CPU simulator written in Rust.
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Jul 24, 2020 - Rust
A program that simulates how a 16-bit CPU works
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Feb 18, 2017 - C
Tiny series: A handwritten CPU of MIPS instruction set.
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Mar 27, 2020 - Verilog
This is a an Arduino code to program a breadboard 8-Bit CPU based on Ben Easter CPU design
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Aug 13, 2020 - C++
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Apr 28, 2017 - Python
A very simple implementation of a general purpose 12 bit RISC CPU for educational purposes.
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May 9, 2020 - VHDL
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Some RISC-V instructions perform writes to 2 destinations, either 2 register or register or program counter. In cases if the source of one sub-operation matches a destination of another one, the order of result output is important. The examples are
jalrand instruction operating with CSRs:riscv/riscv-tests#258
riscv/riscv-tests#263
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