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hardware-description-language
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Hardware Description Languages
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May 25, 2020
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
linux
iot
fpga
zynq
tensorflow
assembly
vhdl
embedded-systems
internet-of-things
hardware-architectures
verilog
xilinx
vivado
tensor
hardware-designs
hardware-acceleration
fpga-accelerator
hardware-description-language
ip-core
tpu
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Jan 5, 2019 - VHDL
SystemRDL 2.0 language compiler front-end
asic
fpga
eda
registers
register-descriptions
systemrdl-compiler
hardware-description-language
design-automation
register-description-language
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Jun 21, 2020 - Python
A core language for rule-based hardware design 🦑
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Jun 23, 2020 - Coq
ACT hardware description language
eda
circuit-simulator
cad
hdl
vlsi
hardware-description-language
design-automation
asynchronous-circuits
vlsi-cad
asynchronous-vlsi
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Jul 8, 2020 - C++
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May 20, 2020 - JavaScript
Code Portfolio -- Collection of Interesting CS and ECE Projects in different languages (C, C++, Python, CPU & GPU Parallel Paradigms, MATLAB, and VHDL) and target hardware with technical reports, and my Vim Config
python
portfolio
machine-learning
cryptography
networking
matlab
vhdl
vim-configuration
video-game
image-processing
data-structures
biometrics
digital-communication
digital-signal-processing
information-security
classwork
exploiting-vulnerabilities
parallel-programming
hardware-description-language
gpu-programming
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Mar 1, 2019 - C
The digital design of computer systems course project, named freeman with respect to the Ross Freeman, the inventor of FPGA, under supervision of Dr. M. Saheb Zamani.
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Jan 21, 2018 - VHDL
design
automation
fpga
vhdl
eda
circuits
electronic
rtl
sistemas
electrical-engineering
ufsc
digitais
digital-systems
quartus
hardware-description-language
ine5406
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Jun 21, 2018 - HTML
SystemRDL command-line control/status register compiler toolchain
asic
fpga
eda
command-line-tool
registers
register-descriptions
systemrdl-compiler
hardware-description-language
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May 18, 2020 - Python
jpt13653903
commented
Jul 21, 2018
The Wiki is outdated. It needs to be brought in line with the TOPLAS and SIPS2018 articles.
- Scanner EBNF
- Parser EBNF
- Verification EBNF
- Remove old junk from the Wiki pages
- Verification section
Flow Based Hardware Simulator
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Mar 18, 2020 - JavaScript
An 8-bit processor in VHDL based on a simple instruction set
processor-architecture
fpga
processor
vhdl
verilog
vivado
hardware-designs
hdl
xilinx-fpga
processor-simulator
hardware-description-language
digital-electronics
altera-fpga
processor-design
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Mar 7, 2019 - VHDL
Parser and Lexer to Hardware Description Language using Prolog
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Jun 3, 2017 - Prolog
A Scheme Inspired Hardware Description Language
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Sep 6, 2018 - Python
Verilog implementation of Brainfuck cpu
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Sep 22, 2018 - PLSQL
A Hardware Description Language for logic gates interpreted by js
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Sep 14, 2016 - JavaScript
A simple VHDL code that describes the hardware needed to implement a vending machine
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Nov 1, 2017 - VHDL
A systemverilog implementation of the data structures: priority queue, queue and stack
system
stack
hardware
open-hardware
priority-queue
data-structures
rtl
verilog
systemverilog
fifo
hdl
system-verilog
hardware-description-language
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Apr 2, 2020 - SystemVerilog
Library code for upcoming RetroClash book
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Jul 5, 2020 - Haskell
Hardware Description Languages
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Jan 7, 2019 - C
building a computer
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Apr 25, 2019 - Assembly
Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone computer hardware platform; Including Virtual machine,Compiler and Operating system.
cpu
compiler
virtual-machine
assembler
operating-system
nand2tetris
computer-architecture
nand
machine-language
hardware-description-language
arithmetic-logic-unit
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Mar 30, 2020 - C++
Implementing a 4-bit Kogge Stone Adder (a type of carry-tree adder) in VHDL using XIlinx Vivado
vhdl
embedded-systems
xilinx-vivado
hardware-description-language
digital-electronics
electronics-engineering
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May 15, 2018 - VHDL
5 stage pipelined risc processor written in SystemC
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Apr 1, 2020 - C++
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Jul 11, 2018 - VHDL
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Oct 31, 2018 - Scilab
This implements a simple median filter on hardware.
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Aug 19, 2019 - SystemVerilog
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What would be workflow for creating and installing external haskell packages? I am running snap from release 1.2. I used to work with cabal in past, but I am out of loop on current packet management in new environment.
Any pointers would be much appreciated.