Here is a simple example for Vivado.

https://github.com/SymbiFlow/fpga-tool-perf/blob/f8438d0447ae808fd1434073b037fa30b274c423/fpgaperf.py#L444-L506

    def vivado_resources(self):
        report_path = self.out_dir + "/" + self.project_name + ".runs/impl_1/top_utilization_placed.rpt"
        with open(report_path, 'r') as fp:
            report_data = fp.read()
            repo

Verilator should only run on Verilog-HDL with proper Verilog file extensions.

maybe a

verilog.lint.include : [".sv", ".v"] //Verilog HDL/SystemVerilog configuration setting

Add command line option, to enable the user to choose which builder he/she wants to use. Suggestion:
--builder BUILDER specify the builded to be used

By adding it, it would allow:

1. Users to actively choose the builder the way to use, without any code change (e.g. editing hdl_checker/builder_utils.py).
2. to separate use cases and make it easier to track bugs that may arise.

The documentation of pyIPCMI contains references and whole sections belonging to the PoC-Library.

Sub tasks:

• Remove documentation snippets referring to PoC content.
• Remove references to PoC.
• Name PoC as an example / use case.
• Review documentation structure / ToC.