mips32

Cross-platform virtual machine for Squeak, Pharo, Cuis, and Newspeak.

Instruction set simulator for RISC-V, MIPS and ARM-v6m

Introducing the new lightweight MIPS Assembler and Disassembler, supporting syntax highlighting, code editing, file dragging and dropping, debug mode, assembly and disassembly, Molokai color matching style. Full platform support including Windows, macOS and Linux. Star now! Keep updating!

Online MIPS32 Simulator Based on Spim

Provide Gentoo binhosts using github infrastructure

A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall

Repositório para as aulas, exercícios e resumos da matéria: organização e arquitetura de computadores (INE5607).

POSIX-compatible tiny multi-threading library for Intel Nios II / Xilinx Zynq-7000

MIPS32 emulation fuzzing

Street Fighter II using MIPS and the DE2-70 development kit.

An ELF parser, which calculates stack usage for embedded mips microcontroller, especially for Microchip's XC32 compiler

A low power, high performance 32-bit, 5-cycle MIPS core that implements a subset of instructions.

Projects that were done for my CS14 (Assembly language) course that used the MIPS assembly language.

Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.

indy: a versatile experimental MIPS emulation library

My attempt at reverse engineering my modem's firmware

💻 MIPS Pipeline Processor simulator

This library is intended to be used with the branchless programming technique which generally plays nicer with RISC systems. Sometimes, pipeline hazards (structural, or data) which can potentially manifest as pipeline stalls, can occur through branch instruction sequences that the compiler cannot avoid. These bubbles can be avoided by using arithmetic instructions instead of branching multiple times. Using bits not only saves memory, but also in most cases, speeds up the logic.

Relatively new toolchain for PIC32 MCUs

A 32-bit MIPS processor developed in Verilog based on pipeline

BUAA Operating System

An implementation of 32-bits MIPS Single Cycle Datapath in Verilog HDL.

🖥️MIPS32 in Verilog

Simple single cycle processor for modified reduced MIPS32 instruction set.

Custom CPU and GPU architectures to run GUI applications on an FPGA.

Port of OpenXcom Extended to OpenDingux 👽

Unconventional MIPS Architecture CPU with Pipeline structure with fewer stalls and advanced units to ensure smallest possible CPI. Designed in Verilog and contains simulation and implementation for Xilinx Basys 3 board

Computer Architecture and Organization