Solutions

1. Convert INO files to CPP

2. Manual prototype declaration

#ifdef DO_NOT_USE
typedef int32_t delaytype;
void thisShouldNotAppearInTheBinary(delaytype timer); // aded manually
void thisShouldNotAppearInTheBinary(delaytype timer) {
  delay(timer);
}
#endif

In https://github.com/freechipsproject/chisel3/blob/master/chiselFrontend/src/main/scala/chisel3/Data.scala#L377:

      requireIsHardware(this, "data to be connected")
      requireIsHardware(that, "data to be connected")

The first error message is incorrect. It should be something like left hand side of the connection.

Collect coverage information at end of tests.

https://www.veripool.org/projects/verilator/wiki/Manual-verilator

1. Pass --coverage option to verilator in makefile
2. Modify c++ test harness to VerilatedCov::write into an output file. There will be one file per test, which should be collected somewhere (this probably needs to be done by test_harness.py)
3. Run verilator_coverage executable,

What would be workflow for creating and installing external haskell packages? I am running snap from release 1.2. I used to work with cabal in past, but I am out of loop on current packet management in new environment.

Any pointers would be much appreciated.

This is the first RISCV core I've been able to get up and running without breaking my head. Much appreciation for the SpinalHDL team for the making this work with Qsys and Avalon. :) (Although SpinalHDL itself puzzling still.)

Where should notes and documentation go? (Is there a wiki?) There's a lot of little things I had to figure out. It would be nice to make it easy to post the notes. One ex

I would like to use icestudio in class e.g. to demonstrate the simulation of logic gates. Ultimatively I would like to create logic tables with the students.

I found following two descriptions but - unfortunately - do not speak spanish:

• https://groups.google.com/forum/#!topic/fpga-wars-explorando-el-lado-libre/E-EwTaCl01Q
• http://haudahau.com/vadedos/?p=1497 also after using google transla

Our Makefile.ghdl doesn't have the usual | tee $(SIM_BUILD)/sim.log at the end of the simulation command line nor any other option to that effect, so it doesn't produce a sim.log file at all.

Auto-generated files
.vscode/c_cpp_properties.json
.vscode/launch.json
contains absolute path, for example:

"configurations": [
        {
            "type": "platformio-debug",
            "request": "launch",
            "name": "PIO Debug",
            **"executable": "/Users/username/Projects/projname/.pio/build/esp32dev/firmware.elf",
            "toolchainBinDir": "/Users/u

[Enter steps to reproduce:]

1. ...
2. ...

Atom: 1.38.2 x64
Electron: 2.0.18
OS: "Manjaro Linux"
Thrown From: platformio-ide package 2.3.1

Stack Trace

Uncaught Error: ENOENT: no such file or directory, lstat '/home/sgh/.atom/init.coffee'

At fs.js:1661

Error: ENOENT: no such file or directory, lstat

The README says:

[...] you'll need an SD card image for your DE10 with a valid installation of Cascade. Cascade can generate this image for you automatically [...]

The obvious question is "how". Is there a command that generates the image?

I have a working DE Nano, it has linux running, it is connected through the Ethernet.
Is this image not sufficient, and Cascade should generate

Expected Behaviour

Odin should compare the titles by name and make sure they match. Also be case sensitive (which I think odin is).

Current Behaviour

Odin uses strcmp thus comparing the names and blank spaces not the tokens.

Possible Solution

Compare the tokens instead of using strcmp

Steps to

As in spec,
EEAR register should save the instruction fetch VA when illegal instruction exception.

We should change code in mor1kx_ctrl_cappuccino.v as follow.

    always @(posedge clk `OR_ASYNC_RST)
     if (rst)
       spr_eear <= {OPTION_OPERAND_WIDTH{1'b0}};
     else if (/*padv_ctrl & exception*/ exception_re)
       begin
	  if (except_ibus_err_i | except_itlb_miss_i

Author Name: Driss Hafdi
Original Redmine Issue: 1624 from https://www.veripool.org

If a variable of the wrong witdth is passed in as a parameter, verilator prints out in its warning the parameter definition location, whereas it would be more helpful to get the reference of the value that was passed in, particularly with bigger design with multiple levels of hierarchy. Here is a

The SCons file is quite "magical" and undocumented at the moment. I needed to find it to understand these points for example:

• how is a PCF file located? which is chosen if there are multiple?
• how are testbench files recognized and treated?
• how are verilog source files recognized and treated?

IMO the second two should be documented in the docs for apio sim and apio build respectiv

It's nice that contrary to the utwente WebSDR software, KiwiSDR makes an attempt at maximizing the use of screen real estate for the waterfall. However at the same time, it makes it frustrating whenever the interface clutters the useful display :/

I'll talk personally but I expect plenty other people would feel the same. The thick, solid top bar feels cumbersome. The top left general informatio

The pre-requisites hidden inside the ariane_setup.sh should probably be moved to README. There is currently no callout to these dependancies.

sudo apt install \

gcc-7 \

g++-7 \

gperf \

autoconf \

automake \

autotools-dev \

libmpc-dev \

libmpfr-dev \

libgmp-dev \

gawk \