Env:

• python 3.8
• capstone 4.0.1
• ubuntu 18.04 (WSL)

Repro:

import capstone
md = capstone.Cs(capstone.CS_ARCH_X86, capstone.CS_MODE_32)
md.detail = True

# case 1
# expected: fstcw  WORD PTR [ebp-0x4] (based on Objdump disassembly which round-trips with GNU as)
for insn in md.disasm(b"\x9B\xD9\x7D\xFC", 0):
    print(insn.address, insn.mnemonic, insn.op_str)

print(

The Readme on the front page makes this reference:

"How can I parameterize my Rocket chip?

By now, you probably figured out that all generated files have a configuration name attached, e.g. freechips.rocketchip.system.DefaultConfig. Take a look at src/main/scala/system/Configs.scala. Search for NSets and NWays defined in BaseConfig. You can change those numbers to get a Rocket core with diff

This is the first RISCV core I've been able to get up and running without breaking my head. Much appreciation for the SpinalHDL team for the making this work with Qsys and Avalon. :) (Although SpinalHDL itself puzzling still.)

Where should notes and documentation go? (Is there a wiki?) There's a lot of little things I had to figure out. It would be nice to make it easy to post the notes. One ex

If this is not the case a page fault should be generated. Right now we generate an instruction access fault.

https://github.com/pulp-platform/ariane/blob/ad70ce1f30dad539e5a365ffe71a02aaf20b397e/src/load_store_unit.sv#L339

Currently the COMMIT_LOG_PRINTF, MEMTRACE_PRINTF, and the DEBUG_PRINTF are executed as chisel prints which are emitted to stderr However you can only have one of these at a time, since they all go to stderr.

We should create C DPI widgets that also direct the logs into files. Preferably this would be some templated thing, since there are lots of things we potentially want to trace ou

The JIT API currently just checks instruction operands and emits the instruction.

• Add simple buffer implementation to collect JIT output
• Add support for labels, and link step
• Add mprotect handling (W^X) so output JIT can be executed
• Add host ABI trampoline for calling JIT with arguments and return value

To ease reviewing the cv32e40p RTL code it would be beneficial to clearly document the retirement policy for various instructions groups: Which instructions will retire in what pipeline stage and how is it guaranteed that instructions retire in program order.

The question came up in relationship with the handling of CSR instructions, see openhwgroup/cv32e40p#262

Adding background to list of syntax styling of editor would allow to use dark syntax themes (like Solarized Dark)

Impact: documentation

Description
We should show an example MDF JSON in addition to defining the fields for people who like to pattern match.

When reading https://ppci.readthedocs.io/en/latest/reference/codegen/registerallocator.html , I was surprised that corresponding .rst file is almost empty: https://github.com/windelbouwman/ppci-mirror/blob/master/docs/reference/codegen/registerallocator.rst , and the contents comes fully from the corresponding .py module, https://github.com/windelbouwman/ppci-mirror/blob/master/ppci/codegen/regist

    at sbt.Defaults$$anonfun$runTask$1$$anonfun$apply$38$$anonfun$apply$39.apply(Defaults.scala:748)
    at scala.Function1$$anonfun$compose$1.apply(Function1.scala:47)
    at sbt.$tilde$greater$$anonfun$$u2219$1.apply(TypeFunctions.scala:40)
    at sbt.std.Transform$$anon$4.work(System.scala:63)
    at sbt.Execute$$anonfun$submit$1$$anonfun$apply$1.apply(Execute.scala:228)

We don't currently have use cases for some combinations of pack widths and instructions. Given the implementation overhead (in terms of complexity and resources) that these generate, it might be worth reviewing which ones we include and which we could discard.