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zedboard

Here are 64 public repositories matching this topic...

bperez77 / xilinx_axidma

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

fpga driver xilinx zedboard axi-dma linux-driver axi-vdma dma-driver xilinx-axi-dma xilinx-axi-vdma userspace-dma fpga-dma

Updated Nov 6, 2021
C

MeowLucian / SDR_Matlab_OFDM_802.11a

📡 Using Software Designed Radio to transmit OFDM QPSK signals at 5 GHz

radio gui zynq packets hardware matlab xilinx sdr zedboard ofdm qpsk preamble ad9361 ieee80211a fmcomms3 fmcomms analog-device 80211 xilinx-zynq

Updated Apr 7, 2018
MATLAB

eliaskousk / parallella-riscv

RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards

zynq linux-kernel rocket-chip gsoc gsoc-2016 zedboard petalinux parallella risc-v rocket-core

Updated Nov 14, 2018
SystemVerilog

MeowLucian / SDR_Matlab_OFDM_802.11n

📡 Using Software Designed Radio to transmit MIMO-OFDM QPSK signals at 5 GHz

Updated Apr 2, 2018
MATLAB

DLX4 / zed_face

zedboard上基于FPGA+ARM的人脸识别智能监控系统。关键词：linux，zedboard，arm，fpga，人脸检测，人脸识别。

c linux fpga face-recognition face-detection zedboard

Updated Jun 7, 2016
C

jiafulow / zedboard-guide

zynq zedboard petalinux

Updated Feb 9, 2016

FloyedShen / mnist_hls

Lenet for MNIST handwritten digit recognition using Vivado hls tool

zynq hls vivado zedboard fpga-accelerator vivado-hls mnist-hls

Updated Jul 22, 2020
Objective-C

Kenji-Ishimaru / polyphony

3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.

fpga gpu verilog zedboard realtime-rendering 3d-graphics-rendering

Updated Oct 3, 2020
Verilog

Goshik92 / SHA256Hasher

SHA-256 IP core for ZedBoard (Zynq SoC)

arm fpga zynq xilinx sha256 vivado systemverilog soc zedboard

Updated Jun 22, 2018
Verilog

MeowLucian / SDR_Matlab_LTE

📡 Using Software Designed Radio to transmit LTE downlink signals at 2.4 GHz

radio gui zynq hardware matlab xilinx sdr iio analog-devices zedboard software-defined-radio ofdm ad9361 fmcomms3 fmcomms xilinx-zynq 64qam

Updated Jul 3, 2019
MATLAB

WangXuan95 / ZedBoard_Tutorial

Vivado+PetaLinux 系统搭建教程 —— 基于 Zedboard

zynq vivado zedboard petalinux block-design soc-fpga zynq-7020

Updated Apr 1, 2022
C

mmattioli / ZedBoard-OLED

Driving the OLED display on the ZedBoard

zynq oled zedboard

Updated Jan 30, 2020
VHDL

MeowLucian / SDR_Matlab_OFDM_802.11a_16QAM

📡 Using Software Designed Radio to transmit OFDM 16QAM signals at 5 GHz

Updated Apr 7, 2018
MATLAB

delhatch / Zynq_UDP

Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.

zynq udp zedboard

Updated Mar 24, 2021
C

MeowLucian / SDR_FM_Radio

📻 Using Software Designed Radio to transmit & receive FM signal

radio station zynq xilinx sdr simulink fm analog-devices zedboard demodulation modulation ad9361 fmcomms3 fmcomms simulink-model xilinx-zynq

Updated Apr 2, 2018
MATLAB

delhatch / VGA_mem_mapped

Memory-mapped VGA display for Xilinx/Zynq/Zedboard, with demo code for using it.

vhdl mandelbrot zedboard vga

Updated Feb 26, 2018
VHDL

sarthak268 / Embedded_Logic_and_Design

Sponsor

This repository contains all labs done as a part of the Embedded Logic and Design course.

Updated Jun 10, 2018

delhatch / Zedboard_Mandel

Mandelbrot generator on the Zedboard. The image is output on the VGA port. Pure Verilog RTL, no ARM core.

verilog zedboard

Updated Jan 19, 2018
VHDL

Goshik92 / fsearch

FastSearch is a project intended to increase the speed of string searching by using the FPGA technology

fpga zynq verilog vivado fpga-soc zedboard bitap

Updated Jun 22, 2018
Verilog

dougbrion / fpga-image-processing

Low latency FPGA based image processing (Zedboard)

fpga image-processing zedboard

Updated Oct 9, 2016
VHDL

zslwyuan / Zedboard_Intergrating_HLS_IP_AND_DDR

This is a project integrating HLS IP and CortexA9 on Zynq. This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART.

tutorial hls ddr vivado zedboard

Updated Sep 2, 2019
VHDL

ugoleone / zedboard_image_processing_pipeline

FPGA based image processing pipeline using zedboard, able to accelerate openCV functions

opencv computer-vision hls image-processing xilinx vivado fpga-soc zedboard hls-video ov7670 xfopencv

Updated Apr 29, 2020
VHDL

arokasprz100 / HDL-Safe

Simple safe lock mechanism written in SystemVerilog.

oled systemverilog hdl zedboard xilinx-vivado zynq-7000

Updated Feb 14, 2020
SystemVerilog

twosixlabs / ultrazed_dev

UltraZed Development

zynq high-performance-computing fpga-soc-linux hardware-acceleration zedboard fpga-accelerator

Updated Mar 16, 2018
C

eliaskousk / parallella-riscv-images

Parallella RISC-V Prebuilt Images

zynq linux-kernel rocket-chip gsoc gsoc-2016 zedboard parallella risc-v board-parallella

Updated Aug 18, 2016

Inception-framework / debugger

A low-latency USB3-based JTAG debugger.

debugger fpga zynq zedboard usb3

Updated Apr 13, 2020
VHDL

Injabie3 / dj-board

SFU - ENSC 452 (Advanced Digital System Design) Term Project: The Ultimate DJ Board using a Zedboard. Also mirrored on SFU CSIL's GitLab.

c vhdl embedded-systems xilinx zedboard xilinx-vivado simon-fraser-university xilinx-sdk

Updated Nov 29, 2018
VHDL

zdzislaw-s / audio-processing

Simple audio processing with ADAU1761

audio fpga zynq hardware xilinx vivado bare-metal zedboard audio-processing adau1761 zedboard-audio-jack

Updated Apr 18, 2020
Tcl

zdzislaw-s / oled-driver-demo

OLED driver demo running on ZedBoard

c-plus-plus sdk zynq hardware animation freertos verilog spi vivado ssd1306 oled-display zedboard xilinx-fpga xilinx-vivado bitstream oled-display-ssd1306 axi4-lite

Updated Jun 24, 2018
PHP

HYSUM-TOBBETU / AES-Encyrption-Verilog-Pipelined-Implementation-128bit

Device: Zedboard xc7z020clg484-1, Clock Rate: 319 MHz, Tool: Vivado 2018.3, Language: Verilog

fpga matrix verilog vivado mds zedboard xor sbox aes-engine clock-rate aes-wrapper rcon-matrices

Updated Feb 1, 2021
Verilog

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