Facilitates building open source tools for working with hardware description languages (HDLs)

mirror of https://git.elphel.com/Elphel/vdt-plugin

Scripts to build and use docker images

VCD file (Value Change Dump) command line viewer for Windows, Linux, OSX

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Python classes to create agnostic wave files for HDL simulator viewer

This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog

This is a test suit spacewire using a model on systemC with a verilog with graphical interface

Template for creating VHDL project using docker

A completely functional encryption decryption model with specially generated Asymmetric key verification

Trabalho de Sistema Digitais II - xr16 é uma arquitetura RISC de 16 bits.

Simulation platform that enables VHDL-style C++ coding. VCD generation for easy debug. VHDL code generation using C preprocessor. Simple risc-V rv32i SoC example, + Risc-V test suite and gcc bare-metal example. Linux (or WSL) / clang or gcc / risc-v toolchain / quartus required

iverilog Extension for Visual Studio Code to satisfy my fantasy of designing building a simple CPU

GTKWave fork with remote control features

🌱 Tool GTKWave for open FPGAs

A repo for CS 3339 students learning verilog

This is a simple FIFO queue implementation in Verilog for the Modern Computer Architectures course (2016-2017) of Harokopio University.

PROGRAMS OF VHDL

Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

Batchfile4iverilog

Command line utilities for GHDL+vivado project management and simulation

Lab exercises of the course F342 Computer Architecture

SystemC eclipse project with embedded and live gtkwave view of traced signals

Containerized open and free development tools for Dynamic Binary Hardware Injection (DBHI)

A tool to invoke ghdl/gtkwave functions, including error highlighting