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verilator
veripoolbot
veripoolbot commented Dec 6, 2019

Author Name: Driss Hafdi
Original Redmine Issue: 1624 from https://www.veripool.org


If a variable of the wrong witdth is passed in as a parameter, verilator prints out in its warning the parameter definition location, whereas it would be more helpful to get the reference of the value that was passed in, particularly with bigger design with multiple levels of hierarchy. Here is a

WezelA
WezelA commented Oct 22, 2019

Using the SystemC statement

head = (head + 1) % 3;

causes the PrintITL to print the line

at t_end: head = ((1 + head_at_t)(31 downto 0) mod 3)(31 downto 0);

in the respective property. Onespin reports this line with the following output:

-E- FIFO.vhi:119:58 Slice expression is out of range.
type: unsigned(1 downto 0)
slice: 31 downto 0
: at t_end: from_re

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