OpenTimer

Repositories

• OpenTimer

  A High-performance Timing Analysis Tool for VLSI Systems

  parallel-computing eda circuit-simulator cad verilog cpp17 circuit-simulation
  C++ 57 162 17 1 Updated Apr 18, 2020

• Parser-Verilog

  A Standalone Structural Verilog Parser

  flex eda verilog cpp17 circuit computer-aided-design vlsi-physical-design
  Verilog MIT 6 11 1 1 Updated Jun 11, 2019

• Parser-SPEF

  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

  eda circuits cpp17 vlsi computer-aided-design vlsi-physical-design sta
  C++ MIT 4 21 2 0 Updated Jan 2, 2019