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Forked from verilog-to-routing/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
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Forked from hamsternz/DisplayPort_Verilog
A Verilog implementation of DisplayPort protocol for FPGAs
Verilog
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631 contributions in the last year
Contribution activity
July 2020
- kgugala/docker-helpers Python
Created a pull request in YosysHQ/yosys that received 1 comment
Add loop iterator declaration in the loop definition
This PR adds possibility to declare loop iterator as a part of the loop declaration (including genvar declaration) e.g:
for(genvar k=...
for(int k=…
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