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Forked from olofk/serv
SERV - The SErial RISC-V CPU
Verilog
EAGLE Library for Custom and Special Electrical/Electronic Components
1 1
Forked from lowRISC/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
SystemVerilog
An SPI/QPI memory controller for ESP PSRAM64H with a Tilelink (TL-UL) slave agent.
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