grep unknown opentitan.fasm  | wc
    557    6127   52651

557 bits isn't too many. Most of these are likely related to the DSP, as 1 DSP is being used:

DSP_L_X66Y110.DSP48.DSP_0.AREG_0
DSP_L_X66Y110.DSP48.DSP_0.BREG_0
DSP_L_X66Y110.DSP48.DSP_0.MASK[45:0] = 46'b1111111111111111111111111111111111111111111111
DSP_L_X66Y110.DSP48.DSP_0.ZADREG[0]
DSP_L_X66Y110.DSP48.DSP_0.ZAL

Here is a simple example for Vivado.

https://github.com/SymbiFlow/fpga-tool-perf/blob/f8438d0447ae808fd1434073b037fa30b274c423/fpgaperf.py#L444-L506

    def vivado_resources(self):
        report_path = self.out_dir + "/" + self.project_name + ".runs/impl_1/top_utilization_placed.rpt"
        with open(report_path, 'r') as fp:
            report_data = fp.read()
            repo

Hello sir, may you please provide new and detailed doc and readme about this project?
This would be a great pleasure by you.
Best wishes.

I have a couple contributions to make to the documentation found at http://www.rapidwright.io/docs/. Is there place to submit these contributions?

Verilator should only run on Verilog-HDL with proper Verilog file extensions.

maybe a

verilog.lint.include : [".sv", ".v"] //Verilog HDL/SystemVerilog configuration setting