netgen

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

An open-source static random access memory (SRAM) compiler.

Massively Parallel Simulator of Optical Coherence Tomography (OCT-MPS)

JKU IIC environment (tools, examples) for Open-Source IC (OSIC) Design for SKY130.

Minimal SKY130 example with self-checking LVS, DRC, and PEX

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).

Netgen Enhanced Binary FIle Bundle is an eZ Platform bundle that provides a field type that reimplements ezbinaryfile field type.

SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA

A simple study showing eZ Platform content consumed by Gatsby via GraphQL

A Python module for generating random network flows problem instances in DIMACS graph format.

Lua modules to work with FEA data

Conda build for netgen mesher

Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel