Here are
32 public repositories
matching this topic...
A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
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May 18, 2020
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VHDL
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
The Antikernel operating system project
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Apr 23, 2020
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Verilog
Development platform for the Espressif ESP32 WiFi/Microcontroller SoC
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Nov 3, 2016
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Eagle
A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.
Small Processing Unit 32: A compact RV32I CPU written in Verilog
FPGA implementation of vaxman's QNICE CPU as a fully fledged 16bit system-on-a-chip
A Modeling and Verification Platform for SoCs using ILAs
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
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Jan 24, 2020
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Verilog
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Apr 7, 2019
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Verilog
TransferCL: an open framework for transfer learning on mobile device
System-on-a-Chip for FPGA, with xr16 RISC core and LCC port
A custom C API for instrumenting Jetson TX1’s SoM and SoC
A ZipCPU SoC for the Nexys Video board supporting video functionality
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Dec 20, 2019
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Verilog
Project about hardware acceleration performance on a Xilinx Zynq-7000 SoC ZC702
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Oct 29, 2019
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VHDL
A kernel-mode driver for exposing Linux like mmap(...) to user-mode applications on Windows for direct physical memory access.
AXI/MIPS SoC developed in VHDL with FreeRTOS port. Capable of running either preemptively or cooperatively.
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Mar 19, 2018
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VHDL
LPP's VHD_Lib is a kind of addon to gaisler's grlib with most Laboratory of Plasma Physics VHDL IPs.
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Nov 26, 2018
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VHDL
Template project for litex-based SoCs
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May 31, 2020
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Python
Mixed-Signal Oscilloscope on Chip
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Oct 15, 2017
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Verilog
Trying to implement a soft core SoC
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Apr 6, 2019
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Verilog
Image Processing Algorithms on System-on-Chip FPGA Devices using a myRIO as hardware and LabVIEW as software
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Jul 8, 2018
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LabVIEW
HTTP request/response parser in C for AVR-based SoC like Arduino
Convolutional Neural Networks for Verilog High-Level Synthesis
System-Verilog implementation of the ACDMA crossbar
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Nov 25, 2018
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SystemVerilog
SOC register access via FUSE
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