Here are
25 public repositories
matching this topic...
Online OR1K Emulator running Linux
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Updated
May 20, 2019
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JavaScript
All CPU and MCU documentation in one place
mor1kx - an OpenRISC 1000 processor IP core
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Updated
Aug 1, 2020
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Verilog
OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
Research Microkernel for Manycores
An OpenRISC 1000 Multicore Virtual Platform
Generating the call graph from elf binary file
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Updated
Jun 23, 2020
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Assembly
An OpenRISC 1000 Instruction Set Simulator
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Updated
Aug 5, 2020
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SystemVerilog
System on Chip verified with UVM
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Updated
Aug 9, 2020
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SystemVerilog
Lisp-based stackless interpreter and platform, including microthreading. Features taken from Lisp and Erlang.
Processing Unit verified with UVM
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Updated
Aug 9, 2020
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SystemVerilog
System on Chip with OpenRISC-32 / OpenRISC-64
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Updated
Aug 9, 2020
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SystemVerilog
Processing Unit with OpenRISC-32 / OpenRISC-64
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Updated
Aug 9, 2020
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SystemVerilog
MPSoC with OpenRISC-32 / OpenRISC-64
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Updated
Dec 23, 2016
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Assembly
OpenCpuX wrapper for the or1kiss OpenRISC ISS
Low-Level Library for Nanvix
Examples of Applications for Nanvix
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Updated
Aug 6, 2020
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Makefile
Baremetal Libraries for Nanvix
FPU verification tool for OpenRISC based on softfloat library
OpenRISC processor IP core based on Tomasulo algorithm
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