If this is not the case a page fault should be generated. Right now we generate an instruction access fault.

https://github.com/pulp-platform/ariane/blob/ad70ce1f30dad539e5a365ffe71a02aaf20b397e/src/load_store_unit.sv#L339

Summary:
A nice-to-have feature is the ability to enable and disable hardware features from the software.

Examples:

• Enable TSO memory consistency
• Enable watchdog timer
• Change predictor behaviors

High-level thoughts:

• Do not use non-standard Control/Status Registers (CSRs). The address space will get too congested, not indexable, messy to assemble for, etc.
• Inst

RISC-V Specification:

• 3.2.2: "URET is only provided if user-mode traps are supported, and should raise an illegal instruction otherwise."

Issue Description:

Executing URET instruction when U mode isn't supported doesn't raise an illegal instruction exception.

Example:

As shown below, the instruction 32'h00200073 (URET) is decoded at time point t##0, where MSTATU

I found two issues with breakpoints while playing around with timertool for #80.

1. Changing a breakpoint does not have an affect on a running program until it is paused and then restarted. Breakpoints are passed to the simulator thread as function arguments (which is definitely necessary), but that means changes to the UI do not affect the simulator until the threads is shut down and restarted.