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Pinned repositories
Repositories
esp-isa-sim
Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
chisel-testers2
Repository for chisel3 testers2 open alpha
dsptools
A Library of Chisel3 Tools for Digital Signal Processing
hwacha
Microarchitecture implementation of the decoupled vector-fetch accelerator
ariane-wrapper
Wrapper for ETH Ariane Core
gemmini-rocc-tests
Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
riscv-sodor
educational microarchitectures for risc-v isa
hammer
HAMMER: Highly Agile Masks Made Effortlessly from RTL
chisel-release
Chisel release tooling
chisel-tutorial
chisel tutorial exercises and answers
chisel-repo-tools
Tools (mostly python3.7, but some python2.7) for accessing GitHub repos via GitHub API
esp-tests
Custom extensions to the RISC-V tests for the UCB-BAR ESP project
nvdla-workload
Base NVDLA Workload for FireMarshal
nvdla-wrapper
Wraps the NVDLA project for Chipyard integration
chisel-gui
A prototype GUI for chisel-development
libgloss-htif
A libgloss replacement for RISC-V that supports HTIF
spec2017-workload
FireMarshal workload for SPEC2017
esp-binutils-gdb
ESP toolchain binutils port
esp-opcodes
Custom extensions to the RISC-V opcodes for the UCB-BAR ESP project
riscv-blas
Custom BLAS and LAPACK Cross-Compilation Framework for RISC-V
