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  • Gisselquist Technology, LLC

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  • Arctic Code Vault Contributor

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  1. A small, light weight, RISC CPU soft core

    Verilog 571 69

  2. A utility for Composing FPGA designs from Peripherals

    C++ 99 6

  3. A configurable C++ generator of pipelined Verilog FFT cores

    C++ 107 14

  4. Bus bridges and other odds and ends

    Verilog 132 18

  5. An Open Source configuration of the Arty platform

    Verilog 80 15

  6. A simple, basic, formally verified UART controller

    Verilog 113 24

584 contributions in the last year

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Contribution activity

September 2020

Created an issue in steveicarus/iverilog that received 1 comment

Assertion failure from within vthread.cc

Consider the following SV design: module top; task test_task; begin fork begin $display("Process #1"); #20 $display ("Process #1 -- completes"); end

1 comment

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