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ghdl

Here are 33 public repositories matching this topic...

ghdl / ghdl

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Revisit CLI syntax

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eine commented Apr 9, 2020

Currently, the architecture of the CLI is based on (sub)commands and options. Commands are expected to be provided as the first argument, and do effectively decide which feature is to be used. OTOH, options provide parameters to the commands. However, there is no syntactical difference, as both commands and options start with -- or -i. As a result, we rely on properly formating --help and on

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Good First Issue

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Replace IEEE libraries with VHDL-2019 packages (Apache license)

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FST and real data type

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olofk / edalize

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An abstraction library for interfacing EDA tools

Updated Aug 19, 2020
Python

suoto / hdl_checker

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Repurposing existing HDL tools to help writing better code

python vim language-server vhdl issue-tracker standalone verilog xilinx syntax-checker systemverilog trademarks hdl modelsim questasim ghdl xilinx-vivado lsp-server coc-nvim vim-ale vivado-simulator mentor-msim hdl-checker emacs-lsp

Updated Aug 9, 2020
Python

Paebbels / JSON-for-VHDL

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A JSON library implemented in VHDL.

parser json fpga simulation vhdl xilinx synthesis lattice fileformat modelsim questasim ghdl

Updated Aug 3, 2020
VHDL

ghdl / docker

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Scripts to build and use docker images

dockerfiles hardware ci simulation vhdl actions verilog synthesis icestorm gtkwave ghdl testbench vunit yosys openocd pnr nextpnr prjtrellis

Updated Jul 24, 2020
Shell

tmeissner / libvhdl

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Library of reusable VHDL components

coverage fpga vhdl verification assertions testbenches ghdl formal-verification osvvm psl

Updated Aug 13, 2020
VHDL

rodrigomelo9 / verifying-foss-hdl-synthesizers

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a project to check the FOSS synthesizers against vendors EDA tools

vivado ise ghdl yosys iverilog verilator quartus pyfpga ghdl-yosys-plugin foss-synthesizers

Updated May 18, 2020
Makefile

tmeissner / formal_hw_verification

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Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog systemverilog ghdl formal-verification yosys psl symbiyosys

Updated Aug 10, 2020
VHDL

tmeissner / psl_with_ghdl

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Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

vhdl assertions ghdl formal-verification yosys psl symbiyosys functional-coverage

Updated Jun 27, 2020
VHDL

tmeissner / cryptocores

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cryptography ip-cores in vhdl / verilog

cryptography fpga vhdl verilog testbenches ghdl

Updated Jul 27, 2020
VHDL

marph91 / icestick-remote

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Remote control in VHDL, which fits on a Lattice icestick.

fpga hardware vhdl ghdl ice40 icestick

Updated Jul 18, 2020
VHDL

qnighy / ghdl-hello

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GHDL Sample Program & Makefile

Updated Dec 17, 2014
VHDL

vhdl-docker-template

YoussefRaafatNasry / vhdl-docker-template

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Template for creating VHDL project using docker

docker vscode gtkwave ghdl vuint

Updated Mar 20, 2020
VHDL

dominiksalvet / risc63

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💻 Custom 64-bit pipelined RISC processor.

Updated Aug 20, 2020
VHDL

marph91 / icestick-uart

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Lightweight UART implementation in VHDL for the lattice icestick

fpga hardware vhdl uart ghdl yosys ice40 icestick

Updated Jul 18, 2020
VHDL

SethGower / dotfiles

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The configuration files for my linux setup on my laptop and desktop.

vim linux dotfiles tmux neovim i3-gaps ghdl polybar configuration-files

Updated Apr 15, 2020
Vim script

eine / ghdl-packaging

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Sources for package management systems to build GHDL

debian archlinux fedora deb rpm pkgbuild msys2 ghdl mingw32 mingw64

Updated Jul 25, 2020
Shell

dbhi / vboard

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Virtual development board for HDL design

vhdl verilog hdl ghdl cosim vpi verilator fli vhpidirect

Updated Jul 27, 2020

eggsactly / VHDL-FIFO

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FIFO implemented in VHDL.

Updated Nov 25, 2017
VHDL

tivaliy / ghdl-jenkins-swarm-slave

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Docker-based Jenkins swarm slave client with GHDL software

docker-container vhdl jenkins-jobs ci-infrastructure ghdl vunit jenkins-swarm

Updated Apr 4, 2017
Shell

umarcor / MSEA

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Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

matlab octave gtkwave ghdl vunit cosim co-simulation

Updated May 10, 2020
VHDL

hargorin / udp_communication

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UDP/IP communication between FPGA and PC

fpga udp ghdl udp-communication ip-communication

Updated Aug 20, 2020

PLC2 / Solution-StopWatch

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Professional VHDL Class Solution - StopWatch

training simulation stopwatch vhdl class rtl xilinx synthesis vivado ghdl plc2

Updated Nov 17, 2019
VHDL

cajt / ghdlsynth-testcase-loa

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A "test" for GHDL Synthesis. Including logs for https://github.com/tgingold/ghdlsynth-beta/issues/87 .

vhdl testcase ghdl loa ghdlsyth

Updated Feb 28, 2020
VHDL

doppioandante / vivado_tools

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Command line utilities for GHDL+vivado project management and simulation

vhdl tcl vivado gtkwave ghdl

Updated Jan 12, 2020
Shell

kamaz08 / System-Wbudowane

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Systemy-wbudowane 2017

vhdl ghdl embeded

Updated Sep 5, 2017
VHDL

vscode-ghdl-interface

johannesbonk / vscode-ghdl-interface

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A tool to invoke ghdl/gtkwave functions, including error highlighting

vscode vscode-extension gtkwave ghdl vscode-plugin ghdl-interface

Updated Jul 23, 2020
JavaScript

guillaumebour / ying

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Ying is a microcontroller based on a 16 bits RISC microprocessor with a 5-stage pipeline.

microcontroller vhdl ghdl

Updated Jun 12, 2018
VHDL

syfluqs / hdl_scratchpad

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VHDL scratchpad

Updated Feb 18, 2020
VHDL

diogratia / pipelined_des

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Pipelined Digital Encryption Standard in VHDL, includes validation testbench

validation vhdl encryption-standard ghdl

Updated Jul 8, 2018
VHDL

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