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@alainmarcel

SureLog - UHDM

  • Santa Clara

Popular repositories

  1. Surelog Public

    Forked from chipsalliance/Surelog

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    C++ 8

  2. UHDM Public

    Forked from chipsalliance/UHDM

    Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format …

    C++ 3 1

  3. Ideas that need engineering-power from the community for UHDM/Surelog/Related topics

    2

  4. Forked from antmicro/verilator

    C++

  5. yosys Public

    Forked from YosysHQ/yosys

    Yosys Open SYnthesis Suite

    C++

  6. antlr4 Public

    Forked from antlr/antlr4

    ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

    Java 1

Repositories

  • Surelog

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    C++ 8 Apache-2.0 29 0 0 Updated Sep 30, 2021
  • UHDM

    Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    C++ 3 Apache-2.0 17 0 0 Updated Sep 29, 2021
  • antlr4

    ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

    Java 0 2,444 0 0 Updated Sep 20, 2021
  • C++ 0 Apache-2.0 4 0 0 Updated Jun 22, 2021
  • 0 9 0 0 Updated Jun 10, 2021
  • sv-tests

    Test suite designed to check compliance with the SystemVerilog standard.

    SystemVerilog 0 ISC 40 0 0 Updated May 30, 2021
  • tsc

    CHIPS Alliance Technical Steering Committee

    0 Apache-2.0 11 0 0 Updated May 25, 2021
  • yosys

    Yosys Open SYnthesis Suite

    C++ 0 ISC 554 0 0 Updated Nov 14, 2020
  • Help_Wanted

    Ideas that need engineering-power from the community for UHDM/Surelog/Related topics

    2 MIT 0 4 0 Updated Oct 14, 2020
  • C++ 0 LGPL-3.0 1 0 0 Updated Feb 13, 2020

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