seldridge
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Contribution activity
March 2021
Created 8 commits in 3 repositories
Created a pull request in chipsalliance/chisel3 that received 2 comments
Don't toggle top.cpp clock and reset on same cycle
Change top.cpp to deassert reset one time unit before the clock asserts. This avoids a simultation race condition if Chisel and a FIRRTL compiler e…
+9
−3
•
2
comments
Opened 2 other pull requests in 2 repositories
chipsalliance/chisel3
1
merged
llvm/circt
1
merged
Reviewed 25 pull requests in 3 repositories
llvm/circt 13 pull requests
- [FIRRTL] Type lowering of aggregate RegResetOP
- [FIRRTL] Parse CircuitTarget and ModuleTarget Annotations
-
[Seq] Proposal for dialect and
regop - [FIRRTL] Type Lowering of subaccess op
- out-of-block uses shouldn't always force temporaries
- [FIRRTL] Blackbox memory connecting wires backwards.
- Remove combinatorial logic from always block
- [FIRRTL LowerTypes] Add FExtModule type lowering
- Constant to generate 'x and 'z
- [FIRRTL] Simpler read port lowering
- Rename module name keywords
- [FIRRTL LowerTypes] Lower wire bundles to individual wires
- [FIRRTL] Split connect error tests from regular tests
chipsalliance/firrtl 7 pull requests
- Fix width of constant propagation of SInt with zero
- Fix cat of zero-width SInt
- Bump previous version for binary compatibility checking
- Add -fpga flag to enable FPGA-oriented compilation strategies (currently for memories)
- Fix CSESubAccesses for SubAccesses with flips
- Create annotation to allow inline readmem in Verilog
- Fix CI Checks
Created an issue in llvm/circt that received 5 comments
[FIRRTL] Disallow Top-level Abstract Reset
The following circuit should be an error. Assumedly, this should be a verification hook added to either a FIRRTL circuit or to a module that is con…
5
comments
Opened 11 other issues in 2 repositories
llvm/circt
6
open
4
closed
- Constant Prop to Avoid False Index Out of Bounds
- [FIRRTL] Memories with Multiple Write Ports Emit as Multiple Drivers
- [FIRRTL] More alias copy propagation
- [FIRRTL] FIRRTL to RTL Memory Lowering Needs to Handle All Read Under Write Behaviors
- [FIRRTL] LowerTypes for Aggregate Register Inits
- [FIRRTL] Handle Large Memories with Depth > 31 bits (Parser) and > 64 bits (IR)?
- [FIRRTL] Memories can be called "mem"
- [FIRRTL] Parse RawString ExtModule Parameters
- Verilog Or Reduction Improperly Inlines Nots
- RTL array_index_inout read vs. write (FIRRTL Memory Lowering Bug)
circt/perf
1
open
2
contributions
in private repositories
Mar 2 – Mar 3