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Add validation for SIMD instructions #327

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ngzhian commented Aug 26, 2020

Preview at https://www.ngzhian.com/simd/core/valid/instructions.html

There are a bunch of todos:

  • where to define v128.const. in syntax/instructions, v128.const is in the SIMD instructions section. in valid/instructions, t.const is defined under "numeric instructions", which already covers v128. Do we need to define v128.const again?
  • the auxiliary definition of packed as a way to map i8 and i16 as they appear in the instruction names to i32 (and the other types to themselves), does that definition look okay?
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\AVGRU ~|~
\TRUNC ~|~
\CONVERT \\
\production{ternary operator} & \vsternop &::=& \SHUFFLE \\

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rossberg Aug 28, 2020

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Why is this vsternop while the others are vunop, vbinop (without the s)? Are vsunop, vsbinop defined somewhere else? (They appear in validation rules.)

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@ngzhian

ngzhian Aug 28, 2020

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My horrible naming convention is:

  • vs* is all the shape-agnostic instructions, like v128.and
  • vi* is all the int-shape instructions, like i32x4.add
  • vf* is all the float-shape instructions, like f32x4.sqrt
  • v* is union of vi* and vf*

vsunop and vsbinop are defined in the production for instructions above, they aren't grouped as part of this "Conventions" section.

I decided to not group them together becase the validation instructions have 2 different matches, t.op which is for vs* family of instructions, and vxx.op, for the vi*, vf*, v* family.(since t matches v128 and vxx matches all the shapes.)

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rossberg commented Aug 28, 2020

Btw, as a heads-up, I'm vanishing off the grid for the next 2 weeks, so this has to be my last review until after.

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ngzhian commented Aug 28, 2020

No problem, have a great time!

@ngzhian ngzhian mentioned this pull request Sep 10, 2020
@ngzhian ngzhian force-pushed the ngzhian:validation-simd branch from 626f641 to e6553f9 Sep 12, 2020
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