lattner
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Pinned
420 contributions in the last year
Contribution activity
September 2020
- [RTL] Add shru, shrs
- [FIRRTL] Improve RegOp/RegInitOp Verification
- Update to MLIR 84a6da67e6b2a7
- [RTL] Add ShlOp.
- [RTL] Add 'and' constant folding case for canonicalization.
- [FIRRTL] Add Circuit Op Verification
- [RTL] Add 'and' idompotent case for canonicalization.
- Update LLVM to 1d3d9b9cd808ef37f3dacd3ada81bff1353cd24b
- Add a Handshake visitor
- Add support for RTL module and instance, update EmitVerilog
Created an issue in llvm/circt that received 6 comments
[RTL] Implement comparisons
The FIRRTL dialect has things like firrtl.lt but there are no corresponding RTL dialect ops for them. The ops should be added and lowerings impleme…
6
comments
- [FIRRTL] Add support for newer verification constructs
- [RTL] Move `rtl.module` outputs to be "result like"
- [RTL Dialect] Teach `rtl.wire` to do fancy things with SSA names
- [RTL Dialect] Make the syntax for the `rtl.wire` op prettier [MLIR enhancement needed]
- [RTL] Implement reduction operators: andr/orr/xorr etc
- [firrtl] Implement more verifier checks for the FIRRTL dialect