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Implementation of a Tensor Processing Unit for embedded systems and the IoT.
VHDL 126 26
An AR Application to plan train track layouts with OpenTrack models using ARCore
Java 1
Fork of a RISC-V compliant CPU, which originated in a project at the HAW Hamburg
VHDL 1
LEGO® compatible train track design with larger radii
ESP32 based SmartWatch with 3-color ePaper and BLE connectivity
C++
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