CHIPS Alliance

Repositories

• rocket-chip

  Rocket Chip Generator

  scala rocket-chip chip-generator chisel riscv rtl
  Scala 674 1,647 187 68 Updated Dec 18, 2020

• treadle

  Chisel/Firrtl execution engine
  Scala Apache-2.0 17 71 20 9 Updated Dec 18, 2020

• verilator

  Forked from verilator/verilator

  Verilator open-source SystemVerilog simulator and lint system
  C++ LGPL-3.0 142 15 0 1 Updated Dec 17, 2020

• chisel3

  Chisel 3: A Modern Hardware Design Language

  scala chip-generator chisel rtl chisel3 firrtl verilog
  Scala Apache-2.0 315 1,583 161 (1 issue needs help) 62 Updated Dec 18, 2020

• firrtl

  Flexible Intermediate Representation for RTL

  compiler hardware firrtl representation transformation intermediate
  Scala Apache-2.0 129 360 138 (2 issues need help) 75 Updated Dec 17, 2020

• caravel-swerv-el2

  Forked from efabless/caravel

  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  Verilog Apache-2.0 66 1 0 0 Updated Dec 16, 2020

• SweRV-ISS
  C++ Apache-2.0 1 4 0 0 Updated Dec 14, 2020

• AIB-specification

  Home of the Advanced Interface Bus (AIB) specification.
  3 12 4 0 Updated Dec 13, 2020

• Cores-SweRVolf

  FuseSoC-based SoC for SweRV EH1

  tools fusesoc swerv
  Verilog 24 80 11 1 Updated Dec 10, 2020

• Cores-SweRV-Support-Package

  Processor support packages
  Python 0 1 0 0 Updated Dec 10, 2020

• dromajo

  RISC-V RV64GC emulator designed for RTL co-simulation
  C++ 20 78 8 1 Updated Dec 9, 2020

• foundation

  Governance-related CHIPS Alliance documents, guides etc.
  0 5 0 0 Updated Dec 7, 2020

• CLA-test-code_spec
  0 0 0 2 Updated Dec 2, 2020

• aib-phy-hardware

  Advanced Interface Bus (AIB) die-to-die hardware open source
  Verilog Apache-2.0 14 58 2 0 Updated Dec 2, 2020

• Cores-SweRV-EH2
  SystemVerilog Apache-2.0 14 59 2 3 Updated Nov 24, 2020

• Cores-SweRV

  SweRV EH1 core

  fpga processor riscv rtl risc risc-v open-source-hardware
  SystemVerilog Apache-2.0 85 360 10 1 Updated Nov 24, 2020

• CLA-test-codeonly
  2 0 0 3 Updated Nov 23, 2020

• Cores-SweRV-EL2

  SweRV EL2 Core

  fpga processor riscv rtl risc-v open-source-hardware fusesoc
  SystemVerilog Apache-2.0 14 61 3 1 Updated Nov 20, 2020

• artwork

  CHIPS Alliance artwork
  0 1 0 0 Updated Oct 27, 2020

• tree-sitter-firrtl

  FIRRTL grammar for tree-sitter

  tree-sitter parser firrtl
  C++ Apache-2.0 0 3 0 0 Updated Oct 14, 2020

• riscv-v-spec

  Forked from riscv/riscv-v-spec

  Working draft of the proposed RISC-V V vector extension
  Assembly CC-BY-4.0 107 0 0 0 Updated Sep 22, 2020

• omnixtend

  OmniXtend cache coherence protocol
  TeX Apache-2.0 8 46 0 0 Updated Sep 3, 2020

• api-config-chipsalliance

  A Scala library for Context-Dependent Evironments
  Scala Apache-2.0 5 8 0 0 Updated Aug 28, 2020

• aib-phy-generator

  AIB Generator: Analog hardware compiler for AIB PHY
  Shell Apache-2.0 5 9 1 0 Updated Aug 22, 2020

• riscv-dv

  Forked from google/riscv-dv

  SV/UVM based instruction generator for RISC-V processor verification
  SystemVerilog Apache-2.0 163 2 0 0 Updated Jun 19, 2020

• rocket-tools

  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  Shell 23 16 3 0 Updated May 6, 2020

• tilelink

  Tilelink specification repository
  Apache-2.0 0 3 0 0 Updated Mar 20, 2020

• Cores-SweRV_fpga
  Tcl Apache-2.0 8 22 5 1 Updated Feb 7, 2020

• dromajo-test

  Built version of the Linux kernel, following the instructions in dromajo/run
  0 0 0 0 Updated Jan 24, 2020

• tools-cocotb-verilator-build
  Makefile 2 12 3 0 Updated Dec 4, 2019