Here are
27 public repositories
matching this topic...
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
Updated
Jul 8, 2020
SystemVerilog
Network on Chip Implementation written in SytemVerilog
Updated
Jul 6, 2020
SystemVerilog
OPAE porting to Xilinx FPGA devices.
Updated
Apr 8, 2020
SystemVerilog
Implementation of the Advanced Encryption Standard in Chisel
Updated
Nov 14, 2019
Scala
Xilinx PCIe to MIG DDR4 example designs and custom part data files
Pothos FPGA computational offload and buffer integration support
Updated
Jun 12, 2015
VHDL
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
Updated
Nov 21, 2017
Verilog
Utility for creating and modifying VHDL bus slave modules
Updated
Feb 17, 2020
Python
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
Updated
Mar 24, 2017
VHDL
Simple single-port AXI memory interface
Updated
Oct 9, 2019
SystemVerilog
Updated
May 5, 2017
Verilog
IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
Updated
Jul 12, 2017
VHDL
Common RTL modules for RgGen
Updated
Jun 30, 2020
SystemVerilog
AXI/MIPS SoC developed in VHDL with FreeRTOS port. Capable of running either preemptively or cooperatively.
Updated
Mar 19, 2018
VHDL
Updated
Jun 5, 2017
SystemVerilog
Hardware and Software Co-design implementations
Hardware-accelerated vectorized gradient descent for linear regression.
Updated
Aug 13, 2018
VHDL
just some files that show one simple way to simulate some axi cycles.
Updated
May 27, 2016
Verilog
Extract AXI (Full, Lite and Stream) interfaces from Verilog source files
PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx
SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2
Synchronous and Asynchronous FIFO with AXI interface
Updated
Nov 20, 2019
SystemVerilog
AMBA AHB 5.0 VIP in SystemVerilog based on UVM
Updated
Nov 27, 2017
SystemVerilog
Reconfigurable Computing Labs
AXI to Peripheral Interconnect
Updated
Oct 2, 2019
SystemVerilog
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