If this is not the case a page fault should be generated. Right now we generate an instruction access fault.

https://github.com/pulp-platform/ariane/blob/ad70ce1f30dad539e5a365ffe71a02aaf20b397e/src/load_store_unit.sv#L339

Summary:
A nice-to-have feature is the ability to enable and disable hardware features from the software.

Examples:

• Enable TSO memory consistency
• Enable watchdog timer
• Change predictor behaviors

High-level thoughts:

• Do not use non-standard Control/Status Registers (CSRs). The address space will get too congested, not indexable, messy to assemble for, etc.
• Inst

This is not strictly related to CV32E40P as the problem seems to be in fpnew, but did anybody verify the operation of CV32E40P with fpnew in verilator?

There is a coding-style in fpnew, which prevents verilator to work. But even if this problem is solved, the simulation is not running due to a deadlog in the div_sqrt unit. The same code runs with Questa/Modelsim without problems!?

It is hard

I have just recently installed RARS as a replacement for RVS and there doesn't seem to be the ability to display the hex and decimal value at the same time.

If there is already a way to do this apologies for the issue.

attached is a screenshot of how RVS handles it