ic

A scalable video sharing service.

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

Windows Sample in C#, C++, Python, LabVIEW and Java

🐌Yet Another Simulation Architecture

Python module to drive DC motors from a Raspberry Pi using the L293D chip

Generate beautiful pinout diagrams for integrated circuits.

Arm Cortex-M0 based Customizable SoC for IoT Applications

🐛UVM verification kits which uses YASA as simulation script

Next.js Internet Computer Starter Template

Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It also includes various common circuits, such as FIFO, RAM, state machine, and so on. All designs have been validated by Testbench and FPGA functions.

Some design examples of Verilog about digital circuits

UVM resource from github, run simulation use YASAsim flow

A list of International Conferences on Integrated Circuit

Recopilación de mis trabajos en el Grado en Ingeniería Informática de la Universidad de Granada (UGR)

[FORK] An NFT standard that leverages the unique properties of the Internet Computer

A clock divider module that uses 4040 chip. It divides by 2; 4; 8; 16; 32; 64; 128; 226; 512; 1024; 2048; 4096.

Set up your GitHub Actions workflow with a specific version of the Internet Computer SDK

tda7419 audio processor python controller

I can communicate with others by typing their portnumber and their ip address. i can sent messages and receive. when i receive a message another gui opens with the message and can communicate with multiple people. when i sent a message another gui open to receive the incoming message

A Candid library for Golang

swiss gds knife

An ASIC running Pong.

A template for the Internet Computer, configured for Gitpod (www.gitpod.io) to give you pre-built, ephemeral development environments in the cloud.

8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

Repositori de les pràctiques de Interfícies de Computadors de la FIB

A template for static websites on the IC

Internet Computer API Client

Eina d'ajuda per a la matèria d'Introducció als Computadors dirigida als estudiants de 1r any de la FIB (UPC).