efabless

Repositories

• open_mpw_precheck
  Python Apache-2.0 12 14 6 1 Updated Jul 21, 2021

• openfpga
  Verilog Apache-2.0 1 5 0 0 Updated Jul 21, 2021

• caravel

  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

  magic yosys caravel picorv32 openroad openram sky130
  Verilog Apache-2.0 101 94 19 7 Updated Jul 17, 2021

• sky130_sram_macros
  SourcePawn Apache-2.0 8 23 2 1 Updated Jul 12, 2021

• OpenLane

  Forked from The-OpenROAD-Project/OpenLane

  NOTE: The master branch is frozen for OpenMPW2. Please direct any PRs to the develop branch. :: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
  Verilog Apache-2.0 121 2 0 1 Updated Jul 8, 2021

• caravel_user_project

  https://caravel-user-project.readthedocs.io
  Verilog Apache-2.0 69 15 15 2 Updated Jun 20, 2021

• caravel_user_project_analog
  Verilog Apache-2.0 20 8 1 0 Updated Jun 20, 2021

• openfpga-2
  Verilog Apache-2.0 1 1 0 0 Updated Jun 17, 2021

• caravel_ibex

  An example project that utilizes caravel user space for an ibex based SoC

  soc caravel ibex openlane mpw-two
  Verilog Apache-2.0 2 1 0 0 Updated May 28, 2021

• open_pdk_techfiles
  Apache-2.0 1 1 0 0 Updated May 17, 2021

• openram_tc_1kb
  Apache-2.0 0 1 0 0 Updated May 11, 2021

• caravel-lite
  Verilog Apache-2.0 7 4 0 0 Updated May 8, 2021

• strive
  Python Apache-2.0 0 2 0 0 Updated May 7, 2021

• web_app_example
  HTML 1 1 0 1 Updated Apr 27, 2021

• silkflow-examples

  Symbiflow Examples with a Silkflow flavor
  Verilog 0 0 0 0 Updated Apr 14, 2021

• skywater-pdk-libs-sky130_fd_io

  Forked from google/skywater-pdk-libs-sky130_fd_io
  Verilog Apache-2.0 4 0 0 0 Updated Mar 24, 2021

• skywater-pdk-libs-sky130_fd_sc_hd

  Forked from google/skywater-pdk-libs-sky130_fd_sc_hd
  Verilog Apache-2.0 13 0 0 0 Updated Mar 24, 2021

• skywater-pdk-libs-sky130_fd_sc_lp

  Forked from google/skywater-pdk-libs-sky130_fd_sc_lp
  Verilog Apache-2.0 4 0 0 0 Updated Mar 24, 2021

• skywater-pdk-libs-sky130_fd_sc_hdll

  Forked from google/skywater-pdk-libs-sky130_fd_sc_hdll
  Verilog Apache-2.0 4 0 0 0 Updated Mar 24, 2021

• skywater-pdk-libs-sky130_fd_sc_hs

  Forked from google/skywater-pdk-libs-sky130_fd_sc_hs
  Verilog Apache-2.0 4 1 0 0 Updated Mar 24, 2021

• skywater-pdk-libs-sky130_fd_sc_ms

  Forked from google/skywater-pdk-libs-sky130_fd_sc_ms
  Verilog Apache-2.0 4 1 0 0 Updated Mar 24, 2021

• skywater-pdk-libs-sky130_fd_sc_ls

  Forked from google/skywater-pdk-libs-sky130_fd_sc_ls
  Verilog Apache-2.0 4 0 0 0 Updated Mar 24, 2021

• skywater-pdk-libs-sky130_fd_sc_hvl

  Forked from google/skywater-pdk-libs-sky130_fd_sc_hvl
  Verilog Apache-2.0 4 1 0 0 Updated Mar 24, 2021

• silkflow

  More straightforward utility for Symbiflow
  Python Apache-2.0 0 0 0 0 Updated Mar 19, 2021

• caravel_mram
  0 0 0 0 Updated Feb 19, 2021

• caravel_fasoc
  Verilog Apache-2.0 0 0 0 0 Updated Feb 17, 2021

• skywater-pdk-central
  Apache-2.0 1 24 0 0 Updated Jan 13, 2021

• ravenna

  32-bit RISC-V microcontroller

  magic open source riscv vlsi risc-v vlsi-design
  C 3 6 0 0 Updated Jan 8, 2021

• dockerized-verification-setup

  This is a dockerized tool chain for running verilog DV customized for the sky130A-based projects.
  Dockerfile Apache-2.0 1 0 0 0 Updated Dec 31, 2020

• sak-deprecated

  SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA

  magic yosys klayout netgen ngspice openroad openlane
  Python Apache-2.0 0 1 0 0 Updated Dec 19, 2020