verilog-code

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Here are 51 public repositories matching this topic...

benitoss / UnAmiga

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Implementation of Amiga 500/1200 in Altera Cyclone IV FPGA

verilog-code

Updated Jun 4, 2019
VHDL

TheSUPERCD / 8bit_MicroComputer_Verilog

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This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This was developed for the Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

verilog verilog-hdl 8bit iverilog verilog-project ben-eater verilog-code ben-eaters-cpu

Updated Jul 27, 2020
Verilog

aut-ce / CE202-LC-Lab-Manual

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Manual and Template Sources of Logic Circuit Laboratory (Verilog Templates)

homework-assignments verilog-code logic-circuit-laboratory

Updated Jun 3, 2021
Verilog

Arjun-Narula / Traffic-Light-Controller-using-Verilog

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the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

traffic verilog vivado verilog-hdl traffic-light traffic-sign-recognition vivado-hls verilog-programs verilog-simulator verilog-project verilog-code vivado-simulator

Updated Jul 18, 2020
JavaScript

aklsh / getting-started-with-verilog

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Verilog modules for beginners

open-source verilog verilog-hdl verilog-snippets verilog-code

Updated May 27, 2022
Verilog

aditeyabaral / DDCO-Lab-UE18CS207

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A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

verilog logic-programming icarus-verilog digital-design computer-organization verilog-code

Updated Apr 17, 2020
Verilog

mihir8181 / VerilogHDL-Codes

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Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

counter fsm asynchronous verilog fifo testbenches verilog-hdl verilog-programs mealy-machine-code moore-machine-code verilog-project fifo-buffer verilog-code n-bit-alu verilogvalidation design-under-test asynchronous-fifo fifo-verilog

Updated May 10, 2019
Verilog

djzenma / RV32IC-CPU

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Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

cpu verilog risc hdl pipeline-processor verilog-hdl risc-v rv32i verilog-snippets pipeline-cpu risc-processor riscv32 riscv-simulator rv32imc verilog-code riscv32im

Updated May 29, 2020
Verilog

mongrelgem / UART-RTL-Physical-Design

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Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2

layout verilog uart hardware-designs uart-interface verilog-code

Updated Sep 3, 2019
Perl

Sanskar777 / QRS-peak-detection-in-ECG-signals-using-verilog

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ecg-signal ecg-qrs-detection verilog-code curve-length-transform qrs-peak-detection

Updated Dec 1, 2019
Verilog

vasanthkumar18 / Cache-Compression

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Cache compression using BASE-DELTA-IMMEDIATE process in verilog

cache project hacktoberfest verilog-project verilog-code bdi-model hardware-project hacktoberfest2021 cache-compression

Updated Jul 16, 2022
Verilog

geraked / verilog-rle

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Verilog Implementation of Run Length Encoding for RGB Image Compression

Updated Jun 28, 2021
Verilog

ukashasohail / MIPS_32bit_SCDP_Verilog

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An implementation of 32-bits MIPS Single Cycle Datapath in Verilog HDL.

mips mips-assembly verilog verilog-hdl mips-architecture mips32 verilog-project verilog-code

Updated Feb 14, 2021
Verilog

YajanaRao / Verilog

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Verilog Programs

Updated Apr 16, 2021
Verilog

mirceanton / VHDL-Decryption

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A small decryption module, written in Verilog, as a university assignment.

verilog decryption verilog-hdl caesar-cipher zigzag-cipher fence-cipher caesar-cipher-algorithm verilog-project scytale-cipher verilog-code

Updated Dec 24, 2020
Verilog

shilinti / Asynchronous-Interface

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The asynchronous interface is spercifically designed for scalable parallel datapaths.

asic asynchronous-programming verilog-code

Updated Sep 13, 2021
Verilog

snbk001 / Verilog-Design-Examples

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Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

verilog testbenches verilog-hdl verilog-programs verilog-project verilog-code verilog-design self-checking