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vivado
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litghost
commented
Feb 28, 2020
grep unknown opentitan.fasm | wc
557 6127 52651
557 bits isn't too many. Most of these are likely related to the DSP, as 1 DSP is being used:
DSP_L_X66Y110.DSP48.DSP_0.AREG_0
DSP_L_X66Y110.DSP48.DSP_0.BREG_0
DSP_L_X66Y110.DSP48.DSP_0.MASK[45:0] = 46'b1111111111111111111111111111111111111111111111
DSP_L_X66Y110.DSP48.DSP_0.ZADREG[0]
DSP_L_X66Y110.DSP48.DSP_0.ZAL
An abstraction library for interfacing EDA tools
fpga
simulation
vhdl
eda
verilog
xilinx
synthesis
vivado
altera
systemverilog
icestorm
lattice
icarus-verilog
modelsim
ghdl
yosys
verilator
riviera-pro
fossi
spyglass
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Updated
Sep 8, 2020 - Python
FPGA Accelerator for CNN using Vivado HLS
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Updated
Nov 29, 2019 - C++
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
cmake
asic
fpga
cpp
verification
rtl
verilog
xilinx
vivado
systemverilog
systemc
unit-tests
hdl
modelsim
uvm
verilator
quartus
testing-rtl
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Updated
Nov 25, 2019 - SystemVerilog
Build Customized FPGA Implementations for Vivado
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Updated
Sep 10, 2020 - Java
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
linux
iot
fpga
zynq
tensorflow
assembly
vhdl
embedded-systems
internet-of-things
hardware-architectures
verilog
xilinx
vivado
tensor
hardware-designs
hardware-acceleration
fpga-accelerator
hardware-description-language
ip-core
tpu
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Updated
Jan 5, 2019 - VHDL
Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code
ctags
vscode
verilog
vivado
systemverilog
icarus-verilog
modelsim
verilog-hdl
iverilog
bluespec-systemverilog
verilator
language-server-client
systemverilog-support
svls
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Updated
Sep 12, 2020 - TypeScript
luyong6
commented
Jun 5, 2020
What is cuckoo_cam?
It is a checkpoint built on xcvu9p-flga2104-2L-e now. Is it possible to build it to other cards?
If it can also be generated by tcl or source RTLs that makes things more easier.
Thanks.
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
fpga
dsp
vhdl
verilog
fast-fourier-transform
xilinx
fft
vivado
altera
cooley-tukey-fft
digital-signal-processing
fast-convolutions
radix-2
integer-arithmetic
route-optimization
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Updated
Aug 14, 2020 - VHDL
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
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Updated
Jan 30, 2020 - Tcl
Verilog Implementation of an ARM LEGv8 CPU
arm
verilog
xilinx
isa
vivado
hazard-detection
ldr
pipeline-cpu
single-cycle
hennessy
patterson
legv8-arm
multi-cycle
arm-legv8-simulator
forwarding-unit
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Updated
Oct 3, 2018 - Verilog
mirror of https://git.elphel.com/Elphel/vdt-plugin
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Updated
Nov 29, 2017 - Java
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
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Updated
Sep 9, 2020 - SystemVerilog
Lenet for MNIST handwritten digit recognition using Vivado hls tool
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Updated
Jul 22, 2020 - Objective-C
Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
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Updated
Aug 15, 2020 - Shell
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
simulation
verilog
vcs
synthesis
vivado
systemverilog
fixed-point
floating-point
icarus-verilog
iverilog
icarus
xrun
synthesizable
xcelium
irun
ncsim
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Updated
Sep 6, 2020 - SystemVerilog
Global Dark Mode for ALL apps on ANY platforms.
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Updated
Sep 11, 2020 - Verilog
a project to check the FOSS synthesizers against vendors EDA tools
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Updated
May 18, 2020 - Makefile
16-bit Adder Multiplier hardware on Digilent Basys 3
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Updated
Aug 1, 2020 - Verilog
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If you speak another language, I would appreciate your help in translating the
README.md.For tables, checklists, or other data that might change, please indicate that that information is in the main README. Otherwise every change to the main README will need to be replicated to the other READMEs.
^ I've tried to do this a bit in the French README. The only thing you need to replicate when