from nmigen import *
from nmigen.back import verilog

class WrappedInstance(Elaboratable):
    def __init__(self):
        self.a = Signal()
        self.b = Signal()

    def elaborate(self, _):
        m = Module()
        m.submodules += Instance("test", o_aout = self.a, o_bout = self.b)
        return m

m = Module()
m.submodules.instan

from nmigen.back import rtlil
from nmigen_soc import csr

csr_mux = csr.Multiplexer(addr_width=16, data_width=8, alignment=8)
csr_mux.add(csr.Element(1, "r"))

print(rtlil.convert(csr_mux))