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instruction-semantics

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JonathanSalwan / Triton

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Triton is a Dynamic Binary Analysis (DBA) framework. It provides internal components like a Dynamic Symbolic Execution (DSE) engine, a dynamic taint engine, AST representations of the x86, x86-64, ARM32 and AArch64 Instructions Set Architecture (ISA), SMT simplification passes, an SMT solver interface and, the last but not least, Python bindings.

reverse-engineering symbolic-execution binary-analysis instruction-semantics program-analysis taint-analysis smt binary-translation
  • Updated Dec 4, 2020
  • C++

lifting-bits / remill

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Missing amd64 instruction semantics for XORPS, XORPD, ANDPS, and ANDPD

pgoodman
pgoodman commented Jun 27, 2018
  • (AMD64 bc5ad 3 (BYTES 0f 57 ff) XORPS_XMMxud_XMMxud (WRITE_OP (REG_256 YMM7)) (READ_OP (REG_256 YMM7)) (READ_OP (REG_128 XMM7)))
  • (AMD64 bf2ac 4 (BYTES 66 0f 57 c9) XORPD_XMMxuq_XMMxuq (WRITE_OP (REG_256 YMM1)) (READ_OP (REG_256 YMM1)) (READ_OP (REG_128 XMM1)))
  • `(AMD64 f6c89 4 (BYTES 41 0f 54 d2) ANDPS_XMMxud_XMMxud (WRITE_OP (REG_256 YMM2)) (READ_OP (REG_256 YMM2)) (READ
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enhancement good first issue help wanted missing instruction semantic

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