risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 592 public repositories matching this topic...
-
Updated
Apr 7, 2021 - Python
-
Updated
Mar 24, 2021 - Verilog
About this question, here is a unified reply.
We need to see this place where one is the definition and load the configuration.
https://github.com/sipeed/MaixPy/blob/master/components/micropython/port/builtin_py/board.py
If you don't provide the configuration, you won't get the concrete variable.
If it is SIPEED published hardware, the appropriate configuration is provided here.
htt
-
Updated
Apr 10, 2021 - C
-
Updated
Apr 10, 2021 - C++
-
Updated
Apr 9, 2021 - C#
We should add some documentation around how to run lint, run RISC-V verification etc. The current top-level Makefile does help here but it'd be useful for this information to be included in the main Ibex documentation set as part of the getting started information.
Try out svlint
-
Updated
Apr 10, 2021 - C
I have just recently installed RARS as a replacement for RVS and there doesn't seem to be the ability to display the hex and decimal value at the same time.
If there is already a way to do this apologies for the issue.
This is discussed a bit more in #456.
Currently, to copy off files from the fs is to 1. mount, 2. chattr, 3. chmod/chown, 4. copy files off. However, this is destructive to the fs (since it changes permissions/users). Instead, there should be a less invasive way to copy off files that doesn't mess with the underlying fs so that people can copy the fs and use it somewhere else.
-
Updated
Dec 11, 2020 - Forth
-
Updated
May 3, 2020 - Verilog
Some RISC-V instructions perform writes to 2 destinations, either 2 register or register or program counter. In cases if the source of one sub-operation matches a destination of another one, the order of result output is important. The examples are jalr and instruction operating with CSRs:
riscv/riscv-tests#258
riscv/riscv-tests#263
Your obj
-
Updated
Apr 9, 2021 - Shell

With Tock running on this board with virtual_uart sitting on top of USB, the Nano 33 BLE is a reasonably promising board to be a standard, well supported Tock board. Additionally, if the board turns out to not be great, the infrastructure which would make the Nano 33 BLE work well would apply to any other board that has the nRF52840 + USB combination.