Haskell to VHDL/Verilog/SystemVerilog compiler
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Apr 14, 2021 - Haskell
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systemverilog
Here are 355 public repositories matching this topic...
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
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Jul 7, 2020 - SystemVerilog
suzizecat
commented
Apr 2, 2021
Input test case
Any sv file.
Describe what is wrong or missing
As far as I can tell, the verible-verilog-kythe-extractor tool cannot directly write its output into a file.
The issue is that it force having a potentially huge buffer in memory.
It would be nice to have the capability to output the result of the kythe extraction directly to an output file without having to rely on
OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
magic
asic
rtl
verilog
systemverilog
vlsi
foundry
fault
yosys
klayout
netgen
system-on-chip
openroad
asic-design
openram
skywater
130nm
soc-design
rtl2gds
qflow
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Apr 13, 2021 - Verilog
An abstraction library for interfacing EDA tools
fpga
simulation
vhdl
eda
verilog
xilinx
synthesis
vivado
altera
systemverilog
icestorm
lattice
icarus-verilog
modelsim
ghdl
yosys
verilator
riviera-pro
fossi
spyglass
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Apr 9, 2021 - Python
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Apr 15, 2021 - SystemVerilog
80186 compatible SystemVerilog CPU core and FPGA reference design
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Mar 19, 2021 - C++
SystemVerilog parser library fully complient with IEEE 1800-2017
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Mar 5, 2021 - Rust
SystemVerilog to Verilog conversion
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Apr 14, 2021 - Haskell
SystemVerilog compiler and language services
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Apr 11, 2021 - C++
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
cmake
asic
fpga
cpp
verification
rtl
verilog
xilinx
vivado
systemverilog
systemc
unit-tests
hdl
modelsim
uvm
verilator
quartus
testing-rtl
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Nov 25, 2019 - SystemVerilog
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
python
rtl
verilog
ieee
systemverilog
hdl
open-source-hardware
pymtl
hardware-generation
open-source-eda
multi-level-modeling
cycle-level-modeling
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Apr 8, 2021 - Python
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
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Oct 19, 2020 - Verilog
hzeller
commented
May 15, 2020
When running the regression, the resulting logs seem to end up in third_party/tests/$TEST/.... This of course is not unnoticed by git, so a git status shows a ton of non-added new files added.
To reproduce:
make
make regression
git status # observe all the filesBuild or test artifacts should never clutter the rest of the code-base (we should regard them as read-only in
Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code
ctags
vscode
verilog
vivado
systemverilog
icarus-verilog
modelsim
hacktoberfest
verilog-hdl
iverilog
bluespec-systemverilog
verilator
language-server-client
systemverilog-support
svls
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Apr 4, 2021 - TypeScript
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
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Apr 12, 2021 - SystemVerilog
tgorochowik
commented
Apr 7, 2021
Currently all the columns have different widths, it does not look very good:
It would be nice to make all the widths equal. We need to think about what can be done so the headers are still equally readable.
Maybe we could make them vertical? Or use some kind of an angl
Repurposing existing HDL tools to help writing better code
python
vim
language-server
vhdl
issue-tracker
standalone
verilog
xilinx
syntax-checker
systemverilog
trademarks
hdl
modelsim
questasim
ghdl
xilinx-vivado
lsp-server
coc-nvim
vim-ale
vivado-simulator
mentor-msim
hdl-checker
emacs-lsp
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Apr 12, 2021 - Python
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
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Apr 14, 2021 - JavaScript
taichi-ishitani
commented
Jul 11, 2019
- AxProt[0]
- 0: Unprivileged access
- 1: Privileged access
- AxProt[1]
- Secure access
- Non-secure access
- AxProt[2]
- Data access
- Instruction access
Code generation tool for configuration and status registers
asic
fpga
eda
rtl
verilog
csr
systemverilog
soc
uvm
ral
axi
amba
apb
register-descriptions
uvm-ral-model
uvm-register-model
wiki-documents
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Mar 13, 2021 - Ruby
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
productivity
pathogen
vhdl
vim-plugins
verilog
xilinx
syntastic
syntax-checker
altera
systemverilog
trademarks
vundle
modelsim
hdlcc-issue-tracker
vimhdl-issue-tracker
vim-hdl
registered-trademarks
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Oct 28, 2019 - Python
Network on Chip Implementation written in SytemVerilog
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Sep 2, 2020 - SystemVerilog
SHA256 in (System-) Verilog / Open Source FPGA Miner
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Mar 10, 2018 - SystemVerilog
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If you speak another language, I would appreciate your help in translating the
README.md.For tables, checklists, or other data that might change, please indicate that that information is in the main README. Otherwise every change to the main README will need to be replicated to the other READMEs.
^ I've tried to do this a bit in the French README. The only thing you need to replicate when