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chisel3
ekiwi
ekiwi commented May 11, 2021

I have been experimenting with replacing the old Enums with the new ChiselEnum in rocket-chip. One important function that is used a lot, but missing from ChiselEnum is isOneOf. This should be fairly straight forward to implement in a type-safe manner.

verilator
vaughnbetz
vaughnbetz commented Dec 17, 2020

Tuo Xie requested the ability to visualize clocking (pins & wires I believe). We should make it easier to visualize subsets of the device routing resource and types of routing nets.

Proposed Behaviour

Add filtering to the rr_nodes displayed (ToggleRR), and to the nets displayed (ToggleNets). I think we should have an option to filter what is shown by node type, node name (segment or pin t

NOTE: The master branch is frozen for OpenMPW2. Please direct any PRs to the develop branch. :: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

  • Updated Jun 6, 2021
  • Verilog

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

  • Updated Dec 8, 2020
  • Haskell

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