Skip to content
@OpenTimer

OpenTimer

A High-performance Timing Analysis Tool for VLSI systems

Popular repositories

  1. A High-performance Timing Analysis Tool for VLSI Systems

    Verilog 282 106

  2. A Standalone Structural Verilog Parser

    Verilog 29 15

  3. A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

    C++ 25 14

Repositories

Top languages

Loading…

Most used topics

Loading…