Andrew Waterman aswaterman

Created 8 commits in 2 repositories

riscv/riscv-pk 5 commits

riscv/riscv-isa-manual 3 commits

Created a pull request in riscv/riscv-isa-manual that received 5 comments
Aug 3

Improve description of interrupt traps

Supersedes #590 This version is much more relaxed but nevertheless covers the important bases of SRET and explicit toggling of xip/xie.

+41 −28 • 5 comments

Reviewed 3 pull requests in 2 repositories

riscv/riscv-isa-manual 2 pull requests

Improve description of interrupt traps Aug 4

Update status of various extensions Aug 3

chipsalliance/chisel3 1 pull request

Added flush capability to Queue Aug 3

4 contributions in private repositories Aug 2 – Aug 4

Andrew Waterman aswaterman

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August 2021

Created a pull request in riscv/riscv-isa-manual that received 5 comments

Improve description of interrupt traps