Pinned
1,289 contributions in the last year
Less
More
Contribution activity
July 2021
Created 9 commits in 1 repository
Opened 1 pull request in 1 repository
Reviewed 31 pull requests in 1 repository
llvm/circt 31 pull requests
- [FIRRTL] Error on Annotations that Do Not Apply
- [FIRRTL][IMConstProp] Proper initialization
- [FIRRTL][ModuleInliner] Properly remove annotations + enable by default
- [FIRRTL] Add a CheckCombCycles pass
- [ExportVerilog] Add option to force wires in event control exprs
- [FIRRTL][GCT] Generate Binds for Grand Central Interfaces
- [Comb] Narrow addition operation to Bits that are observed
- [NFC] Eliminate simple canonicalizer
- Use mlir::parallel*, not llvm::parallel*, NFC
- [FIRRTL] Find lowest common ancestor of two modules in the instance graph
- [Comb] Canonicalize extract(cat(..)) into cat(extract(..)).
- [FIRRTL] Try to get windows compiling
- [SV] Adds a VerbatimAttr to emit verbatim text in extern module parameters
- [ExportVerilog] Inline ReadInOutOp
- [Comb] Compare Strength Reduction
- [ExportVerilog] Emit bind expressions.
- [SV] Add Concurrent Assertions ("assert property" and friends)
- [Seq] Add a more general-purpose [RegOp]
- [FIRRTL] Update Subfield op string fieldName to integer fieldIndex
- [FIRRTL] Allow firrtl.constant of type Clock, Reset, AsyncReset
- [FIRRTL][SV] Add names/labels to side effect stmts
- [FIRRTL] Add folders for no-effect casts
- [Calyx] Add Enable and Sequential Ops.
- Removed intermediate wire between instances and output operations
- [HW] Support type aliases in Struct and Union ops.
- Some pull request reviews not shown.
Created an issue in llvm/circt that received 7 comments
remove EmitVerilog/sv-structs.mlir integration test
Rationale: Integration tests are expensive to maintain and run. Struct emission is already handled by a unit test. We need integration tests for co…
7
comments
Opened 2 other issues in 1 repository
45
contributions
in private repositories
Jul 5 – Jul 19