A C++11 simulator for a variety of CDN caching policies.

SST Architectural Simulation Components and Libraries

Haystack is an analytical cache model that given a program computes the number of cache misses.

cache analysis platform developed at Emory University and CMU

Source code for the evaluated benchmarks and proposed cache management technique, GRASP, in [Faldu et al., HPCA'20].

A graphics tracing and replay framework to explore system-level effects on heterogeneous CPU+GPU memory systems.

This cache simulator is used in order to simulate substitutions in cache using replacement policies (FIFO and LRU) and write back into the cache (using the write-allocate policy).

Computer architecture project - Cache simulator with LRU replacement policy

Direct Mapped and N-Way set associative cache Simulator in C/C++ for L1 cache in Processors

A simple cache simulator

A survey on architectural simulators focused on CPU caches.

AUT Computer Architecture Cache Simulator project

A cache simulator for RISC-V architecture. Made using Python 3

OpenGraph is an open-source graph processing benchmarking suite written in pure C/OpenMP. Integrated with Sniper simulator.

Set of MIPS assembly programs to help us find a secret cache configuration (cache size, block size and associativity).

code 2018

Contains implementations of cache-optimized and external memory algorithms.

A modular implementation of three level Cache Hierarchy

Source code for the evaluated benchmarks and proposed cache management technique, GRASP, in [Faldu et al., HPCA'20].

PKU computer organization and architecture memory hierarchy simulator LAB

cache simulator

Cache Organization and Performance Evaluation

WPI CS2011 Assembly Assignments for B-term 2017

Simple cache simulator built using Java.

This C project is a cache simulation of a CPU containing L1D, L1I and L2 caches. It takes an image of memory and a memory trace as input, simulates the hit/miss behavior of a cache memory on this trace, and outputs the total number of hits, misses and evictions for each cache type along with the content of each cache at the end.

Allows user to simulate two types of a one level, write-through cache with a first-in, first-out (FIFO) replacement algorithm to record the number of memory reads and writes and cache hits and misses.

A loop test performance simulator for cache memories

Simulator for queueing systems and LRU caches