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verilog_systemverilog.vim Public
Forked from vhda/verilog_systemverilog.vim
Verilog/SystemVerilog Syntax and Omni-completion
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November 2021
Created an issue in MikePopoloski/slang that received 1 comment
Empty constraint conditionals not allowed due to empty concatenation error
This may be a whack-a-mole scenario. The following code gets a parse error, but I think it would ideally be accepted since the curly is a constrain…
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