SpinalHDL

Repositories

• VexRiscv

  A FPGA friendly 32 bit RISC-V CPU implementation

  cpu fpga vhdl riscv verilog soc spinalhdl
  Assembly MIT 190 1,095 46 6 Updated May 6, 2021

• SpinalHDL

  Scala based HDL

  scala fpga vhdl rtl verilog
  Scala 153 732 51 13 Updated May 5, 2021

• SaxonSoc

  SoC based on VexRiscv and ICE40 UP5K

  riscv rtl soc
  Scala MIT 21 84 9 0 Updated May 4, 2021

• openocd_riscv

  Forked from Dolu1990/openocd_riscv

  Spen's Official OpenOCD Mirror
  C GPL-2.0 367 21 4 0 Updated May 4, 2021

• SpinalDoc-RTD

  The sources of the online SpinalHDL doc

  documentation spinalhdl
  Python 18 11 5 4 Updated Apr 24, 2021

• SpinalTemplateSbtDependencies

  An SpinalHDL project example which use VexRiscv git as a dependency
  Scala 1 2 0 0 Updated Apr 12, 2021

• SpinalTemplateSbt

  A basic SpinalHDL project
  Scala 18 26 1 0 Updated Apr 12, 2021

• Spinal-bootcamp

  Forked from jijingg/Spinal-bootcamp

  SpinalHDL-tutorial based on Jupyter Notebook
  Jupyter Notebook 17 13 0 0 Updated Apr 10, 2021

• SpinalWorkshop

  Labs to learn SpinalHDL
  Scala 17 57 4 0 Updated Apr 7, 2021

• buildroot-spinal-saxon
  C 1 1 0 0 Updated Mar 25, 2021

• SpinalDoc

  SpinalHDL documentation assets (pictures, slides, ...)
  HTML 11 18 1 0 Updated Mar 16, 2021

• linux
  C 1 0 0 0 Updated Mar 15, 2021

• u-boot

  Forked from u-boot/u-boot

  "Das U-Boot" Source Tree
  C 1,881 0 0 0 Updated Dec 30, 2020

• opensbi

  Forked from riscv/opensbi

  RISC-V Open Source Supervisor Binary Interface
  C 151 1 0 0 Updated Nov 3, 2020

• buildroot

  Forked from buildroot/buildroot

  Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.
  Makefile 1,340 0 0 0 Updated Nov 3, 2020

• embench-iot

  Forked from embench/embench-iot

  The main Embench repository
  C GPL-3.0 49 0 0 0 Updated Jul 8, 2020

• docker
  Dockerfile 3 0 0 1 Updated Jun 18, 2020

• CocotbLib
  Python MIT 4 10 1 0 Updated Jun 18, 2020

• SpinalTemplateMill

  Forked from typingArtist/SpinalTemplateMill

  A simple SpinalHDL demo project based on Mill
  Scala 1 0 0 0 Updated Jun 12, 2020

• SpinalCrypto

  SpinalHDL - Cryptography libraries

  cryptography scala crypto fpga aes vhdl md5
  Scala MIT 10 17 1 0 Updated Jun 8, 2020

• SpinalTemplateGradle

  A basic SpinalHDL project, configured with Gradle instead of SBT
  Scala 0 1 0 0 Updated Dec 15, 2019

• sd_device

  Forked from fusesoc/sd_device

  SD device emulator from ProjectVault
  Verilog Apache-2.0 2 1 0 0 Updated Dec 4, 2019

• zephyr

  Forked from zephyrproject-rtos/zephyr

  Primary GIT Repository for the Zephyr Project
  C Apache-2.0 2,765 0 0 0 Updated Apr 21, 2019

• VexRiscvRegressionData

  Used to store heavy data required to run full VexRiscv regressions
  Assembly 4 0 0 0 Updated Apr 21, 2019

• coremark

  Forked from eembc/coremark

  CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
  C 134 0 0 0 Updated Apr 21, 2019

• VexRiscvSoftcoreContest2018
  Verilog Apache-2.0 14 50 0 0 Updated Dec 16, 2018

• riscv-compliance

  Forked from riscv/riscv-arch-test
  Assembly 90 0 0 0 Updated Nov 18, 2018

• VexRiscvSocSoftware
  C 12 11 0 0 Updated Sep 20, 2018

• riscv-formal

  Forked from SymbioticEDA/riscv-formal

  RISC-V Formal Verification Framework
  Verilog ISC 64 3 0 0 Updated Aug 28, 2018

• SpinalBaseProject-OLD-
  Scala 4 11 0 0 Updated Dec 18, 2017