OpenHW Group

Popular repositories

1. cva6

   The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

   SystemVerilog 1.3k 322

2. cv32e40p

   CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

   SystemVerilog 501 213

3. core-v-verif

   Functional verification project for the CORE-V family of RISC-V cores.

   Assembly 115 75

4. core-v-docs

   Documentation for the OpenHW Group's set of CORE-V RISC-V cores

   76 50

5. force-riscv

   Instruction Set Generator initially contributed by Futurewei

   C++ 72 23

6. cv32e40x

   4 stage, in-order, compute RISC-V core based on the CV32E40P

   SystemVerilog 41 13