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Antmicro
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vtr-verilog-to-routing Public
Forked from verilog-to-routing/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
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DisplayPort_Verilog Public
Forked from hamsternz/DisplayPort_Verilog
A Verilog implementation of DisplayPort protocol for FPGAs
Verilog
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382 contributions in the last year
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January 2022
Created 6 commits in 5 repositories
Created a pull request in litex-hub/litex-boards that received 3 comments
antmicro-datacenter updates
This PR fixes clock pin location and extends eth reset time (required for the ksz9031 phy used on the board)
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