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- 5 discussions answered
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1,078 contributions in the last year
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July 2021
Created 60 commits in 5 repositories
Created a pull request in chipsalliance/chisel3 that received 7 comments
refactor github action
This PR refactor CI container out of GitHub Action to reduce docker maintenance effort. Borrow Verilator CI by @ekiwi from chiseltest Contributor C…
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7
comments
Opened 12 other pull requests in 6 repositories
chipsalliance/chisel3
2
closed
2
open
1
merged
sequencer/arithmetic
2
open
1
merged
chipsalliance/api-config-chipsalliance
1
open
chipsalliance/firrtl
1
open
ucb-bar/chisel-testers2
1
open
freechipsproject/chisel-testers
1
open
Reviewed 11 pull requests in 3 repositories
chipsalliance/chisel3 6 pull requests
chipsalliance/firrtl 4 pull requests
chipsalliance/espresso 1 pull request
Created an issue in chipsalliance/firrtl that received 2 comments
Multi-dimension IO connection bug
Checklist Did you specify the current behavior? Did you specify the expected behavior? Did you provide a code example showing the problem? Did…
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2
comments
Opened 2 other issues in 2 repositories
chipsalliance/chisel3
1
open
OpenXiangShan/XiangShan
1
open
Answered 5 discussions in 1 repository
chipsalliance/chisel3
chipsalliance/chisel3
- 为什么在声明Wire/Reg的时候需要考虑Bundle的方向?(If a bundle is declared as an IO, it is necessary to specify all directions, but is it possible to declare Wire/Reg without considering the directions?)
- Can DeadCodeElimination, CommonSubexpressionElimination, ConstantPropagation, etc. be turned off ?
- Why do modulus(%) and compare(===/<=/>=) operators combinations lead to firrtl.FirrtlInternalException?
- Is there any way to directly access the IR node when having the corresponding annotated target?
- chiseltest with mill as the building tool
10
contributions
in private repositories
Jul 10 – Jul 23